I have done a bit of digging and have come up with a couple of articles on
oxide treatment. Here are the links:
https://dl.dropboxusercontent.com/u/89802638/Oxide_vs_Oxide_AlternativesFeb14.pdf
https://dl.dropboxusercontent.com/u/89802638/Oxide_vs_Oxide_AlternativesMar14.pdf
From what I can make out the oxide grows a crystalline structure that provides
micro voids for the resin to squish into. It also acts as a passivation layer
for the copper. It does not etch the copper surface per se. The Feb2014 article
also explains that a properly passivation layer is important to prevent water
formation under heat and pressure. If there is absorbed water due to poor
passivation, then that could possibly account for additional losses. A quality
issue perhaps.
I also found a link to MEC web site. They supply oxide alternative MEC Vbond
which is a subtractive process which actually etches the copper to roughen the
surface. On this link below they show a good cross-section picture of black
oxide VS their oxide alternative treatment. The pictures clearly shows that
oxide is grown over the underlying copper surface as a separate layer, where as
the oxide alternative actually does roughen the surface of copper.
http://www.mec-co.com/en/product/electronic-substrate/sekisou/
So far I am not convinced, and ready to conclude the additional loss
experienced is due to additional roughness of the copper itself.
Bert Simonovich
Signal/Power Integrity Practitioner | Backplane Specialist | Founder
LAMSIM Enterprises Inc.
Web Site: http://lamsimenterprises.com
Blog: http://blog.lamsimenterprises.com/
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Havermann, Gert
Sent: 11-Nov-16 11:36 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
I think that the oxide treatment isn't just "adding" an oxide layer, it
oxidates the Copper itself and this oxidation isn't homogenious, thus leaving a
rough Copper to oxide barrier. I read in another paper (unfortunately I forgot
the name) that the impact on loss for oxide treatments also depends on the
processing time. The longer the oxidation, the rougher the surface.
Unfortunately I have never found the time to investigate this in depth.
BR
Gert
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Orin Laney
Sent: Friday, November 11, 2016 4:48 PM
To: dmarc-noreply@xxxxxxxxxxxxx; billh@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
"Cuprous oxide (Cu2O) is a red to brown p-type semiconductor with a temperature
dependent resistivity. The resistivity also depends on the method of formation,
but a range of 25 ohm-cm to 10^4 ohm-cm is representative. Suffice to say that
copper oxide resistivity is greater than that of metallic copper by a factor
exceeding at least a million." From "Analysis and Application of Transmission
Line Conductors", section 3.8.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Friday, November 11, 2016 7:19 AM
To: billh@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
Hi Bill,
From data I'd seen, I believed that additive oxide treatments didn't affect
loss since they added a non-conductive rough layer that shouldn't affect the
conductor properties, more like adding a dielectric layer. Oxide alternatives,
on the other hand, are subtractive treatments and should affect the conductor
significantly. I've believed that (additive) oxide treatments won't increase
loss while (subtractive) oxide alternatives would. I never had the opportunity
to test that directly. One issue that bothered me, however, was "How would I
know the difference when looking through a microscope?" That was never
resolved either.
Lee's data suggests additive oxide treatments do increase loss just like
subtractive oxide alternatives. That's actually more satisfying, since it
means I can tell from cross-section the effect of roughness, regardless of how
it's done. It seems copper oxide is more conductive than I thought.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Bill Hargin (Nan Ya, USA)
Sent: Thursday, November 10, 2016 8:29 PM
To: leeritchey@xxxxxxxxxxxxx; dmarc-noreply@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
It's pretty well established that roughness influences loss, and that oxide
treatment influences roughness.
What am I missing here?
Bill Hargin
Director of North American Sales and Marketing Nan Ya Copper-Clad Laminates
billh@xxxxxxxxxxxxx ▪ 425-301-4425 ▪ Skype: bill.hargin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lee Ritchey
Sent: Thursday, November 10, 2016 11:13 AM
To: dmarc-noreply@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
I have cross sections of the two PCBs and the surface roughness is readily
visible between the two. My guess is that assuming the roughening process is
non-conducting is probably not quite correct.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Thursday, November 10, 2016 10:59 AM
To: leeritchey@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
Hi Lee,
Your second sentence is different than my understanding. Gary Brist's paper
"High frequency conductor loss impact of oxide and oxide alternative processes"
concluded that "oxide treatments are not a primary factor in affecting loss",
which made sense to me since oxide isn't a conductor. Are you sure there
wasn't something else that changed between the two PCB's?
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lee Ritchey
Sent: Thursday, November 10, 2016 10:38 AM
To: dmarc-noreply@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
Jeff,
Sounds right to me. I have measured data on the same PCB made by two different
US fabricators, one using Atotech Bondfilm to enhance adhesion during
lamination and the other using "brown oxide". There is a substantial
difference in measure loss between the two, with Bondfilm being lower in loss.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Friday, November 4, 2016 9:21 AM
To: leeritchey@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
Sorry Lee, but some clarifications:
1) RTF is the standard for domestic U.S. vendors, not necessarily so for other
markets.
2) "Oxide" treatments don't affect insertion loss, oxide alternatives (OA) do.
I believe most are using OA treatments, but am not sure. If you're concerned
about loss, you'll want to know exactly what your vendors are using. And/or,
you'll need to measure the final product to be sure.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lee Ritchey
Sent: Friday, November 04, 2016 9:11 AM
To: dmarc-noreply@xxxxxxxxxxxxx; carson.au@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
Reverse treat copper is the "standard copper" of the current industry.
Smooth copper is usually called VLP or HVLP. Our tests show that the
contribution to loss of the copper roughness is visible, but not one of the big
hitters. See our DesignCon paper of 2013. Yes, as Jeff points out,
fabricators normally roughen the copper with one of the oxide treatments.
We know that a finish such as Atotech Bondfilm does not do that and we specify
it on our fab drawings.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Friday, November 4, 2016 7:23 AM
To: carson.au@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
The only benefit I know of for smoother copper (besides decreased insertion
loss) is that RTF etches better than standard copper due to the grain
structure, possibly giving better impedance control. In general, smoother
copper makes the design less mechanically robust and is especially troubling on
outer layers because of rework issues. But, there are designs using it on all
layers and configurations so you should be able to incorporate it where needed.
When using smooth copper, be especially careful to measure insertion loss to
compare simulations against actual - vendors may roughen the copper using
adhesion treatments (OA, or oxide alternative) turning your beautiful smooth
copper into sandpaper.
I agree with Lee that if you aren't designing servers (long channels) it's
probably a moot point. Today's equalization seems to do a very good job of
compensating for deterministic issues such as insertion loss, vias, and
Fiberweave effect.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Carson Au
Sent: Thursday, November 03, 2016 1:01 PM
To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
If loss isn't usually the problem, does that mean usually smooth copper usually
doesn't have to be considered in the design (or are there more benefits to
smooth copper than just lower loss?) Lee, what are the top problems in modern
SERDES layout in your opinion (besides the fibre weave effect)?
On Fri, Nov 4, 2016 at 3:21 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
wrote:
Before I would do any of that, I would do some analysis to see whatpairs!!
the losses would be if normal striplines are used. My experience is
that this extra work would not be necessary.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Loyer, Jeff (Redacted sender "jwloyer" for DMARC)
Sent: Thursday, November 3, 2016 8:16 AM
To: carson.au@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
I think you'd have to void the layers above or below your signal traces.
For instance, I can imagine routing the longest lengths on the
outermost layers of the "core" of a build-up stackup and voiding
layers above those traces to allow me to widen the traces (they would
also be relatively thick, further lowering loss). You'd want a solid
plane above them somewhere, but it doesn't have to be the adjacent
layer. You'd also have to be careful to specify smooth copper on
those layers, else the manufacturer will probably undo your great
efforts by putting rough copper on them.
Jeff
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Carson Au
Sent: Thursday, November 03, 2016 5:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HDI and SERDES Channels
Hi Experts,
From my understanding, HDI build-up layers require thin prepreg
layers, leading to very thin trace widths for 100ohm differential
impedance control
- and your high speed serial links would suffer great conductor loss.
How do you mitigate against this?
If your design has many build-up layers with thin build-up layers on
either side of your stripline, then it is impossible to even get
something like 100um (4mil) trace widths for your 100 ohm differential
Regards,
Carson
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu