Hi Lee,
Your second sentence is different than my understanding. Gary Brist's paper
"High frequency conductor loss impact of oxide and oxide alternative processes"
concluded that "oxide treatments are not a primary factor in affecting loss",
which made sense to me since oxide isn't a conductor. Are you sure there
wasn't something else that changed between the two PCB's?
Jeff Loyer
-----Original Message-----
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Sent: Thursday, November 10, 2016 10:38 AM
To: dmarc-noreply@xxxxxxxxxxxxx
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Subject: [SI-LIST] Re: HDI and SERDES Channels
Jeff,
Sounds right to me. I have measured data on the same PCB made by two different
US fabricators, one using Atotech Bondfilm to enhance adhesion during
lamination and the other using "brown oxide". There is a substantial
difference in measure loss between the two, with Bondfilm being lower in loss.
-----Original Message-----
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Sent: Friday, November 4, 2016 9:21 AM
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Subject: [SI-LIST] Re: HDI and SERDES Channels
Sorry Lee, but some clarifications:
1) RTF is the standard for domestic U.S. vendors, not necessarily so for other
markets.
2) "Oxide" treatments don't affect insertion loss, oxide alternatives (OA) do.
I believe most are using OA treatments, but am not sure. If you're concerned
about loss, you'll want to know exactly what your vendors are using. And/or,
you'll need to measure the final product to be sure.
Jeff Loyer
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Sent: Friday, November 04, 2016 9:11 AM
To: dmarc-noreply@xxxxxxxxxxxxx; carson.au@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
Reverse treat copper is the "standard copper" of the current industry.
Smooth copper is usually called VLP or HVLP. Our tests show that the
contribution to loss of the copper roughness is visible, but not one of the big
hitters. See our DesignCon paper of 2013. Yes, as Jeff points out,
fabricators normally roughen the copper with one of the oxide treatments.
We know that a finish such as Atotech Bondfilm does not do that and we specify
it on our fab drawings.
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Sent: Friday, November 4, 2016 7:23 AM
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Subject: [SI-LIST] Re: HDI and SERDES Channels
The only benefit I know of for smoother copper (besides decreased insertion
loss) is that RTF etches better than standard copper due to the grain
structure, possibly giving better impedance control. In general, smoother
copper makes the design less mechanically robust and is especially troubling on
outer layers because of rework issues. But, there are designs using it on all
layers and configurations so you should be able to incorporate it where needed.
When using smooth copper, be especially careful to measure insertion loss to
compare simulations against actual - vendors may roughen the copper using
adhesion treatments (OA, or oxide alternative) turning your beautiful smooth
copper into sandpaper.
I agree with Lee that if you aren't designing servers (long channels) it's
probably a moot point. Today's equalization seems to do a very good job of
compensating for deterministic issues such as insertion loss, vias, and
Fiberweave effect.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Carson Au
Sent: Thursday, November 03, 2016 1:01 PM
To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HDI and SERDES Channels
If loss isn't usually the problem, does that mean usually smooth copper usually
doesn't have to be considered in the design (or are there more benefits to
smooth copper than just lower loss?) Lee, what are the top problems in modern
SERDES layout in your opinion (besides the fibre weave effect)?
On Fri, Nov 4, 2016 at 3:21 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
wrote:
Before I would do any of that, I would do some analysis to see whatpairs!!
the losses would be if normal striplines are used. My experience is
that this extra work would not be necessary.
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Sent: Thursday, November 3, 2016 8:16 AM
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Subject: [SI-LIST] Re: HDI and SERDES Channels
I think you'd have to void the layers above or below your signal traces.
For instance, I can imagine routing the longest lengths on the
outermost layers of the "core" of a build-up stackup and voiding
layers above those traces to allow me to widen the traces (they would
also be relatively thick, further lowering loss). You'd want a solid
plane above them somewhere, but it doesn't have to be the adjacent
layer. You'd also have to be careful to specify smooth copper on
those layers, else the manufacturer will probably undo your great
efforts by putting rough copper on them.
Jeff
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On
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Sent: Thursday, November 03, 2016 5:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HDI and SERDES Channels
Hi Experts,
From my understanding, HDI build-up layers require thin prepreg
layers, leading to very thin trace widths for 100ohm differential
impedance control
- and your high speed serial links would suffer great conductor loss.
How do you mitigate against this?
If your design has many build-up layers with thin build-up layers on
either side of your stripline, then it is impossible to even get
something like 100um (4mil) trace widths for your 100 ohm differential
Regards,
Carson
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