In a message dated 3/12/2004 4:59:34 PM Pacific Standard Time, weirsp@xxxxxxxxxx writes: Mike, if you would be so kind as to indulge me here, I would like further details on the sort of situation that justified BC for ESD control. Can you cite ballpark numbers where absent BC, the plane impedance was too high and a destructive event was only correctable by pulling the impedance down with BC? ******** Steve: I'll attempt to be detailed enough in my response to hopefully put this subject to bed. Some of my comments are not directly solely to you, but to the less initiated on on SI List..... On more than a dozen boards that were experiencing both soft and hard failures, using BC was ONE of the correcting factors that eliminated all ESD susceptibility. As I noted in my earlier comments on this thread, I use multiple techniques in consort to correct deficiencies in a given board. When I am called in to correct an EXISTING problem, the client is usually in deep schedule trouble, is losing their clients, and/or is losing market share. They demand (and need) an immediate and absolute fix for their problems with an immediate turnaround. The typical project I am called in to FIX has already spent four to six weeks trying to correct deficiencies with in-house staff, and used from one to three other (lower priced) consultants (at $85-$125/hour) who have also failed to correct the problems (sometimes over several months). My rates are 3-4 times higher, but I only spend 4-32 hours to correct the problems (100% success over 19 years, >98% client repeat rate). I'm usually then retained to critique 4-10 other tasks/projects based on my successful resolution of their problems. I have guided the design of hundreds of NEW boards with the goal of total compliance first time--every time in both functional performance and all regulatory compliance requirements with a success rate of >98% on the first shot and 100% with an iteration on the errant few. Specifically for ESD, I have generally coupled the low impedance, sacrificial nature, of multiple-layer chassis ground rings around the board edges with BC (preferably two sandwiches) as an effective fix. Note that I do NOT insist on either of these techniques if the operating environment does not portend the need. If there are other layout deficiencies that I find, I of course recommend additional corrective action. I always define a sequencial order of corrective actions with an assigned priority of expected beneficial impact, generally supported with modeling and analysis to bound performance. Invariably, I have achieved correction for the original problems and also reduced radiated emissions by 6 dB to >30 dB (the latter for boards with poor initial layouts). The technical justification for using BC for reduced ESD susceptibility is multifaceted. First, it yields a low PDS impedance over a very broadband range which helps to control the IC electrical operating environment for common-mode voltage (CMV) injection above ~40 MHz. If you have ever done work with RF tuned tanks, you will be aware that a high C:L ratio for a given resonance will yield lower Q circuits. This is a major (and unheralded) benefit of BC. The thinner the dielectric between the planes, the greater the impact of the dielectric losses. The low-Q effect is to lower the response to physically dictated board resonances. And yes, of course, multiple bulk capacitors and selected small ceramics are still required to handle the lower frequency range, and they will also impact where those resonances occur. Nevertheless, the bottom line is that the low-Q resonances offered by BC sandwiches help prevent unexpected and abberant EMI behavior. Now, from the view of the IC, the power plane, the ground plane, AND the signal reference planes (since they should be ground or power) are all tightly coupled with BC usage so that any injected CMV is strongly attenuated above ~40 MHz. THIS IS A VERY GOOD THING!!!! The IC tends to see ONLY normal-mode and/or differential-mode signals as intended, even in the presence of externally injected transients (ESD events) AND other impinging radiation that is then observed by the IC as CMV!!! For perfect PDS and signal decoupling (close, but no cigar), the IC would not see any perturbation. Think about it. Mike Michael L. Conn Owner/Principal Consultant Mikon Consulting Cell: 408-821-9843 *** Serving Your Needs with Technical Excellence *** ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu