Let me comment on this again. I doubt that there is a general answer with regard to connecting grounds or not.=20 In my opinion the real interesting aspect of ESD design is to really understand which trace, which net and which IC input or output is affected by ESD and how the process first unfolds electromagnetically and then logically within the system. Using the knowledge on the sensitivity of PINs in the design helps avoiding softerrors. This type of information is much more specific than the overall connection of some grounds, more cost efficient than shielding and can be obtained by quantifying the systems response to currents and voltages (pulses as seen by a trace when ESD is applied to the enclosure) when those are injected into specific nets, IC PINS, heatsinks and other suspect locations. Now knowing the sensitivity of I/O pins to softerror causing pulses, one learns which traces to be very careful with. This takes the black magic out of ESD, well at least parts of it. David Pommerenke Associate Professor Electromagnetic Compatibility Group University Missouri-Rolla 1870 Miner Circle, Rolla MO 65409 ph: 573 341 4531 573 341 5835 fax: 573 341 4532 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu