[SI-LIST] Re: ESD is a low frequency event -really??
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'steve weir'" <weirsp@xxxxxxxxxx>,Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>,"'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 16 Mar 2004 15:37:10 -0800
Steve,
I would propose modifying your circuit a little bit,
vsource 1 0
R1 1 12
L1 12 13
CX 13 23
* remove CY1 13 0
R2 1 22
L2 22 23
* remove CY2 23 0
*add the following
R3 1 32
L3 32 33
Inoise 23 0
Rshunt 33 23a
Lshunt 13a 23
The R3/L3 represent the chassis and the Inoise is the ESD discharge injected
into the logic ground branch.
The question then becomes whether making the Rshunt/Lshunt very small (dead
shorts between chassis and logic ground) and R3/L3 very small (gigantic
chassis metal cage vs. copper PCB planes) makes the differential noise
between 23 and 13 even smaller by steering the current through branch R3/L3
instead of R1/L1 and CX.
What do you think ?
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Tuesday, March 16, 2004 2:14 PM
To: Chris.Cheng@xxxxxxxxxxxx; 'si-list@xxxxxxxxxxxxx'
Subject: Re: [SI-LIST] Re: ESD is a low frequency event -really??
Chris, I agree with most of your points here. The way that I look at this
problem is as a network of parallel LC shunts between the PCB planes, both
power and ground and the chassis. So, definitely I agree that more shunts
will do a better job of limiting differential potential.
The behavior of the BC is to shunt between those networks. You can run a
very quick SPICE model by taking three non-ideal capacitors in a classic
line to line and line to ground ( ie X + 2Y ) filter configuration, and
tolerance the values. In our case the X capacitor is the BC. Place an
impedance, resistive and/or inductive in series with each line and then
monitor both the CMV, and the DMV across frequency for a noise source fed
into both of the impedances:
vsource 1 0
R1 1 12
L1 12 13
CX 13 23
CY1 13 0
R2 1 22
L2 22 23
CY2 23 0
The common mode voltage may be observed at either node 13, or 23. The
differential mode is across 13 and 23. Imagine 13 as a point on a voltage
plane and 23 as a nearby point on a ground plane.
Now, if we make CX really small, then the matching of the LPF networks
determines the differential mode conversion. By increasing the value of
the X capacitor, we can swamp out the differences and greatly improve the
common mode to differential conversion caused by the network mismatches,
which is to say our immunity.
But how much improvement do we need over ordinary dielectric and when? I
would like to figure out for myself if and when high cost BC is justified
at design-time as opposed to as a big band-aid for a customer who can't
ship an improperly designed product. I don't personally know the answer,
and was hoping that Mike would provide some numbers or more specific
examples.
Regards,
Steve.
At 01:33 PM 3/16/2004 -0800, Chris Cheng wrote:
>I think the question raise by Doug experiment is whether those isolated
>chassis rings can help or decrease your ESD immunity.
>
>If you notice Doug's experiment, there is literally no edge or peripheral
>coupling (there is simply no "walls" on the chassis plane to be near the
PCB
>edges) and yet substantial noise is injected into the PCB (probably through
>the plane capacitance between the chassis and logic planes). Then it will
be
>even more beneficial to provide more connection between the chassis and
>logic planes to allow the discharge to leak our from the PCB logic planes
to
>chassis. See it in another way, for all the tight chassis connection you
>provide for your peripheral ring, you are better off shorting those
>connections directly to logic planes to provide the lowest possible
>impedance between the chassis and logic at as many point as possible.
>
>If you believe the charge injection really is coming from the peripheral of
>the PCB and therefore you want to isolated it with the preferential chassis
>conduction ring, then why would you still need the BC ? After all, the
>isolation is achieve by forcing the discharge current through the chassis
>ring and not the BC logic planes.
>
>So the question is, do you really want low or high impedance between
chassis
>and logic planes at the peripheral ?
>Doug's experimental data suggest the former, you are suggesting the later.
>
>I have no doubt with BC and correct discrete you can achieve a close to
>ideal PDS response for your PCB all the way to GHz as you said but the
>question is how can that improve the complete path when the bottle neck
>happens at the package design ? If you claim is indeed core noise related
>EMI problem injected into the system, don't you think the radiation will be
>even worst on the package than the PCB given the well establish 100MHz
choke
>point on the package ? I can understand a hired gun like you will have
>limited control on the package design by the time they bring you in to fix
>the problem, but that does not mean the proper fix should be on the PCB
>instead of on die or package.
>
> >The IC tends to see ONLY normal-mode and/or
> >differential-mode signals as intended, even
> >in the presence of externally injected
> >transients (ESD events) AND other impinging
> >radiation that is then observed by the IC
> >as CMV!!!
>
>I would think tightly coupling the image current/return of the signal to
the
>CMV disturbance so that the signal
>and its return cancel out the CMV will be a better solution.
>
> >BC can indeed improve performance in those
> >signal routings where the signal path
> >transitions layers to the opposite side
> >of a BC sandwich without the potential
> >need for added return current vias
>
>I would think the performance will be even better if you simply not use any
>BC sandwich and allow the image current flow through the antipad on the
>reference plane when the signal switch to the other side.
>
>At the end of the day, whichever company I worked for or helping out get
>benefit from using the cheapest and simplest solution to get the product
out
>the door and I just have no mea culpa about not using BC at all. If you
have
>to resort to use BC as a fix while I don't, who get the cost benefit ?
>I understand your claim of not using BC all the time but I do not see the
>benefit of using BC if the signal reference and die/package decoupling are
>done right.
>
>
>-----Original Message-----
>From: MikonCons@xxxxxxx [mailto:MikonCons@xxxxxxx]
>Sent: Monday, March 15, 2004 12:59 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: ESD is a low frequency event -really??
>
>Specifically for ESD, I have generally coupled the low impedance,
>sacrificial
>nature, of multiple-layer chassis ground rings around the board edges with
>BC
>(preferably two sandwiches) as an effective fix. Note that I do NOT insist
>on
>either of these techniques if the operating environment does not portend
the
>
>need. If there are other layout deficiencies that I find, I of course
>recommend additional corrective action. I always define a sequencial order
>of
>corrective actions with an assigned priority of expected beneficial impact,
>generally
>supported with modeling and analysis to bound performance. Invariably, I
>have
>achieved correction for the original problems and also reduced radiated
>emissions by 6 dB to >30 dB (the latter for boards with poor initial
>layouts).
>
>The technical justification for using BC for reduced ESD susceptibility is
>multifaceted. First, it yields a low PDS impedance over a very broadband
>range
>which helps to control the IC electrical operating environment for
>common-mode
>voltage (CMV) injection above ~40 MHz. If you have ever done work with RF
>tuned tanks, you will be aware that a high C:L ratio for a given resonance
>will
>yield lower Q circuits. This is a major (and unheralded) benefit of BC. The
>thinner the dielectric between the planes, the greater the impact of the
>dielectric losses. The low-Q effect is to lower the response to physically
>dictated
>board resonances. And yes, of course, multiple bulk capacitors and selected
>small
>ceramics are still required to handle the lower frequency range, and they
>will also impact where those resonances occur. Nevertheless, the bottom
line
>is
>that the low-Q resonances offered by BC sandwiches help prevent unexpected
>and
>abberant EMI behavior.
>
>Now, from the view of the IC, the power plane, the ground plane, AND the
>signal reference planes (since they should be ground or power) are all
>tightly
>coupled with BC usage so that any injected CMV is strongly attenuated above
>~40
>MHz. THIS IS A VERY GOOD THING!!!! The IC tends to see ONLY normal-mode
>and/or
>differential-mode signals as intended, even in the presence of externally
>injected transients (ESD events) AND other impinging radiation that is then
>observed by the IC as CMV!!! For perfect PDS and signal decoupling (close,
>but no
>cigar), the IC would not see any perturbation.
>
>Think about it.
>
>Mike
>
>Michael L. Conn
>Owner/Principal Consultant
>Mikon Consulting
>Cell: 408-821-9843
>
>*** Serving Your Needs with Technical Excellence ***
>
>
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