[SI-LIST] Re: Decoupling for PLL
- From: steve weir <weirsp@xxxxxxxxxx>
- To: leeritchey@xxxxxxxxxxxxx, "Istvan Novak" <istvan.novak@xxxxxxxxxxxxxxxx>, "zhangkun 29902" <zhang_kun@xxxxxxxxxx>
- Date: Mon, 30 Aug 2004 11:10:24 -0700
Lee,
I agree that most of the mfg. application notes for PLL filtering are bunk,
and can actually make matters much worse. I have seen peaky LC filters in
app notes for years from many mfgs. Each time I have pressed for where
these filter designs came from, no one could justify the particular
implementations. So, our experience is similar on that count.
However, without characterizing for SSO conditions, I think there is
considerable exposure to assuming that reaching a particular noise level on
the digital rail alone will be sufficient. I have worked with too many
mixed signal devices where digital noise fed through to sensitive analog
circuitry when the analog Vcc was not filtered CORRECTLY ie without a giant
peak, with an impedance to block those return currents.
As Chris rightly points out, any given PLL design is going to have
different sensitivity to noise spectrum. So the right answer as to what is
required, is "it depends". Now, how do we resolve this for first pass
success? My answer is either characterize or decouple. If we can't
characterize before first pass design, then there is little safe choice
other than provide for the decoupling filter, characterize at proto and
then conditionally stuff. The only remaining agony is how far down in
frequency we have to go. Fortunately, the design of most VRMs is to
provide the lowest possible equivalent shunt resistance. So, filtering
below 10-50KHz should not be necessary.
Regards,
Steve.
At 08:33 AM 8/30/2004 -0700, Lee Ritchey wrote:
>Istvan,
>
>I'd be delighted to get a data sheet from an IC manufacturer that stated
>how much noise a PLL can tolerate on its supply pin. On most analog ICs we
>get specifications such as power supply rejection ratio that quantify the
>problem. But not digital, which is usually where the PLLs are.
>
>When I do find a part with such a spec, the tolerance for noise on Vdd is a
>number significantly larger than 10 mV.
>
>Any supply that supports single ended CMOS logic needs very low ripple in
>order to make sure that ripple noise doesn't cause logic 1 failures. For
>2.5V logic, ripple in excess of 25 millivolts is too much, so, when the
>supply is designed to support this, the PLL is okay.
>
>Once again, when we add extra networks to the supply system, we are dealing
>with symptoms rather than the problems. In my experience, these networks
>are being put in without first determining if there is a problem that needs
>to be fixed. This is followed by not making sure that the network does fix
>the problem.
>
>In application notes, these networks are being included out of knee jerk
>response to a large collection of rules of thumb. To demonstrate this, I
>have scope traces of a 2.4 GB/S serial link that was designed with the
>manufacturer's ferrite solution in the power lead. The waveform is not
>great. In fact, it fails bot jitter and voltage margin tests. When the
>ferrite bead is removed, the eye diagram met all jitter and noise margin
>specs.
>
>When the vendor rep was presented with this data, he was surprised and
>correctly observed that it was time to stop putting ferrite beads in the
>power leads. Further questioning revealed that no measurements had ever
>been made by the vendor to insure the beads were of value.
>
>Moral of the story, if you see ferrite beads recommended in the supply
>leads of components, insist on seeing the analysis or lab measurements that
>demonstrate they help, not harm.
>
>
>
>Lee W. Ritchey
>Speeding Edge
>P. O. Box 2194
>Glen Ellen, CA 95442
>Phone- 707-568-3983
>FAX- 707-568-3504
>
>I just used the energy it took to be angry to write some blues.
>Count Basie
>
>
> > [Original Message]
> > From: Istvan NOVAK <istvan.novak@xxxxxxxxxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>; zhangkun 29902 <zhang_kun@xxxxxxxxxx>
> > Cc: <a.ingraham@xxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > Date: 8/29/2004 3:19:50 PM
> > Subject: Re: [SI-LIST] Re: Decoupling for PLL
> >
> > Lee,
> >
> > I fully agree that the first line of defence is to create a
> > quiet main supply rail for EMI and power quality reasons.
> > Secondly, it would be very good to have more data
> > from chip makers in terms of how much noise the chip's
> > PLL supply pin can live with.
> >
> > The only extra consideration, which sometimes will result in a
> > different optimum for a main supply rail versus PLL input design,
> > namely a separate filter for the PLL analog pin, is when the
> > system considerations end up with significantly different noise
> > requirements for the main supply rail versus the PLL supply pin.
> > It is not uncommon to have smain supply rails in high-speed
> > systems, where you can easily live with 100mV noise or more.
> > And there are PLLs where the recommended noise on the supply
> > pin may be 10mV or less. You may say: use a different chip,
> > where the PLL can live with more noise on the supply pin; and this
> > is the way if there is a choice; sometimes, however, the designer
> > will find no alternative chips. Frequency range considerations
> > may also call for separate filtering. On a differential signaling
> > system, a common-mode noise contents below a MHz may
> > be tolerable up to a couple of hundred mV magnitude,
> > but the PLL's low-frequency bandwidth is the most sensitive
> > where it can pick up noise and increase jitter.
> >
> > Regards,
> > Istvan
> >
> >
> > ----- Original Message -----
> > From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
> > To: "zhangkun 29902" <zhang_kun@xxxxxxxxxx>; "Istvan Novak"
> > <istvan.novak@xxxxxxxxxxxxxxxx>
> > Cc: <a.ingraham@xxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > Sent: Sunday, August 29, 2004 5:08 PM
> > Subject: [SI-LIST] Re: Decoupling for PLL
> >
> >
> > > All of this discussion around how to isolate PLLs from Vdd noise speak
>to
> > a
> > > symptom, namely, too much noise on Vdd.
> > >
> > > True, it is possible to add all manner of networks such as have been
> > > discussed over the last few days, but these still only treat the
>symptom.
> > >
> > > It is a far better strategy to do a good job designing the power
>subsystem
> > > so that ripple is held to a minimum. This is necessary to satisfy noise
> > > budgets and to help make passing EMI tests easier anyway.
> > >
> > > The reason for these networks in the first place is that manufacturer's
> > > applications notes did not and still do not properly advise a user on
>how
> > > to design a good power subsystem. Once this is understood, and it
>isn't
> > > such a tough topic, ripple will be well within the tolerances of well
> > > designed PLLs.
> > >
> > > To support these statements, log onto www.procket.com. You will see a
> > > terabit router that has hundreds of PLLs in it as well as 5000+ 2.4 GB/S
> > > serial links. All of the PLLs are connected directly into the power
>plane
> > > from which they draw power. There are no ferrite beads or other
>networks
> > > in their power leads.
> > >
> > > All that was necessary was to design the decoupling, including plane
> > > capacitance, such that ripple was less than 20 millivolts to make them
>all
> > > happy.
> > >
> > > It would be far better if advice on how to achieve a maximum ripple
> > > amplitude were given in applications notes along with how much ripple a
> > PLL
> > > can tolerate. This would allow predictable designs to be done.
> > >
> > > Among the reasons not to use ferrite beads in this manner are: they add
> > > extra components and they carry the risk of presenting the PLL with a
>high
> > > impedance source of power potentially making the PLL more unstable
>rather
> > > that more stable.
> > >
> > > In almost all cases I have seen, ferrite beads are band aids for designs
> > > and problems that are not well understood and carry the risk of making
> > > designs worse rather than better. When things were slower, the tended
>to
> > > do no harm, because the ICs involved were slow enough that the
>degradation
> > > in power supply impedance didn't much matter. That is no longer true.
> > >
> > > Lee W. Ritchey
> > > Speeding Edge
> > > P. O. Box 2194
> > > Glen Ellen, CA 95442
> > > Phone- 707-568-3983
> > > FAX- 707-568-3504
> > >
> > > I just used the energy it took to be angry to write some blues.
> > > Count Basie
> > >
> > >
> > > > [Original Message]
> > > > From: zhangkun 29902 <zhang_kun@xxxxxxxxxx>
> > > > To: Istvan NOVAK <istvan.novak@xxxxxxxxxxxxxxxx>
> > > > Cc: <a.ingraham@xxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > > > Date: 8/30/2004 12:00:11 AM
> > > > Subject: [SI-LIST] Re: Decoupling for PLL
> > > >
> > > > Istvan
> > > >
> > > > The input of PLL is clock of 77MHz and the output is clock of 622MHz.
>I
> > > measure the noise at 77MHz, 154MHz, 231MHz, ... , 622MHz, and so on.
> > > >
> > > > We have found that there is some problem below 250KHz. My solution is
>to
> > > use some beads of high impedance in low frequency domain. I have not
>check
> > > the result.
> > > >
> > > > Best Regards
> > > >
> > > > Zhangkun
> > > > 2004.8.29
> > > >
> > > > ----- Original Message -----
> > > > From: Istvan NOVAK <istvan.novak@xxxxxxxxxxxxxxxx>
> > > > Date: Sunday, August 29, 2004 9:23 pm
> > > > Subject: Re: [SI-LIST] Re: Decoupling for PLL
> > > >
> > > > > Zhangkun,
> > > > >
> > > > > When you say "harmonic frequency", do you mean the
> > > > > output frequency of PLL? Most of the time the output
> > > > > frequency is much higher than the PLL's filter bandwidth,
> > > > > which is usually in the hundreds of kHz. PLLs tend to
> > > > > be sensitive to noise on their analog supply pin at or
> > > > > below the filter bandwidth. Have you also compared the
> > > > > noise below 1MHz?
> > > > >
> > > > > Regards,
> > > > > Istvan
> > > > >
> > > > >
> > > > > ----- Original Message -----
> > > > > From: "zhangkun 29902" <zhang_kun@xxxxxxxxxx>
> > > > > To: <a.ingraham@xxxxxxxx>
> > > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > > Sent: Sunday, August 29, 2004 5:34 AM
> > > > > Subject: [SI-LIST] Re: Decoupling for PLL
> > > > >
> > > > >
> > > > > > Andy
> > > > > >
> > > > > > I use spectrum analyzer to measure the power ground noise in
> > > > > frequencydomain. At almost all the harmonic frequency, the
> > > > > amplitude with 0 ohm
> > > > > resistor is less of 3db than that with bead.
> > > > > >
> > > > > > The pre-filter power is of plane pair.
> > > > > >
> > > > > > Best Regards
> > > > > >
> > > > > > Zhangkun
> > > > > > 2004.8.29
> > > > > >
> > > > > > ----- Original Message -----
> > > > > > From: Andrew Ingraham <a.ingraham@xxxxxxxx>
> > > > > > Date: Saturday, August 28, 2004 9:48 pm
> > > > > > Subject: [SI-LIST] Re: Decoupling for PLL
> > > > > >
> > > > > > > Zhangkun,
> > > > > > >
> > > > > > > Some PLLs can be very sensitive to tiny amounts of noise. They
> > > > > > > are, after
> > > > > > > all, analog devices.
> > > > > > >
> > > > > > > When you say the noise difference is only 3dB, (1) that might be
> > > > > > > just enough
> > > > > > > of a difference to cause a problem, if your circuits were just
>on
> > > > > > > the edge
> > > > > > > of misbehaving; and (2) if you are measuring and comparing
> > > > > > > broadband noise,
> > > > > > > it is a meaningless comparison. The PLL is particularly
>sensitive
> > > > > > > to noise
> > > > > > > at particular frequencies, and you may need to look specifically
> > > > > > > for those
> > > > > > > frequencies. A broadband noise measurement could mask the
> > > > > > > frequencies that
> > > > > > > are causing the problem. Even a spectrum analyzer might, if you
> > > > > > > don't know
> > > > > > > what frequencies to look for.
> > > > > > >
> > > > > > > Another thought: does connecting the instruments to measure
> > > > > the noise,
> > > > > > > significantly affect the circuit? Maybe simply connecting
>probes
> > > > > > > reducesthe noise enough to stop that PLL from misbehaving (while
> > > > > > > the other two PLLs
> > > > > > > continue to misbehave).
> > > > > > >
> > > > > > > How clean is the pre-filtered power? Is it a plane?
> > > > > > >
> > > > > > > Is there anything else of an analog nature on this board?
> > > > > > >
> > > > > > > Regards,
> > > > > > > Andy
> > > > > > >
> > > > > > >
> > > > >
> > > > >
> > > > >
> > > >
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