[SI-LIST] Re: Decoupling for PLL
- From: steve weir <weirsp@xxxxxxxxxx>
- To: zhang_kun@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 26 Aug 2004 10:28:48 -0700
At 12:04 AM 8/27/2004 +0800, zhangkun 29902 wrote:
>Dear all
>
>I have a question about decoupling for PLL. In one of our PCB, there are
>three PLL. PI decoupling circuit is used. When the inductor is used, the
>PCB does not work. When resistor of 0 ohm is used, the PCB work well.
This is due to the inductor peaking. You can capture your clock output and
put it through an FFT, and also capture the PS voltage and put it through
an FFT. The problem frequency(s) should correlate. PLLs can be sensitive
to rather low frequency noise, some all the way down to the KHz.
Steve.
>I have measured the power ground noise. The power ground noise in the two
>situation is different of 3db, which could be ignored. The power ground
>noise is very small. The power ground is about -50dbm at the harmonic
>frequency of PLL.
>
>It is obvious that the key element is the decoupling circuit. However,
>when I measure power ground noise, I could not find the obvious
>difference. Please give me some advice. Is there anything which could not
>be measured at PCB level?
>
>Best Regards
>
>Zhangkun
>2004.8.27
>
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