[SI-LIST] Re: Decoupling for PLL
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'steve weir '" <weirsp@xxxxxxxxxx>, "'istvan.novak@xxxxxxxxxxxxxxxx '" <istvan.novak@xxxxxxxxxxxxxxxx>, "'leeritchey@xxxxxxxxxxxxx '" <leeritchey@xxxxxxxxxxxxx>, "'zhangkun 29902 '" <zhang_kun@xxxxxxxxxx>
- Date: Mon, 30 Aug 2004 02:11:29 -0700
I truly wish when there is a PLL noise problem, it can go away with a few
sentences of description and a few words of advices from a public forum. The
last time I had a problem, me and Bill Gunning stared at the circuits for
six months and keep scratching our heads. :-(
Not all PLL's are created equal and their jitter response due to power
supply noise can varies widely. I've seen smart designer that design VCO
gain that can be dynamically adjust and the loop filter response can be make
within 10X of the reference frequency. The unintended benefit is the filter
can take care of power noise jitter frequency almost up to near the
reference frequency. I have also seen people built power regulator within
the PLL to damp down any low frequency component that the loop filter cannot
take care. To take these PLL designs and proclaim there is no need for
external power filter for ALL PLL is plain wrong. I have seen a few 10's of
mV hitting the PLL at the right frequency can knock the PLL out of spec.
Just ask Ray how his old boss learn the importance of power filtering
especially the need for the damping resistor. I guarantee you that the
discussion between me and his boss is worst than the worst debate I had over
here before I convince him the importance of the resistor. And he learned
quickly after a few bad things happened since then.
There is just no way you can pick the optimal filtering combo without some
serious testing on power noise frequency vs. jitter experiment, surely not
by just a few discussions in the SI-list.
That said, I very suspicious about the fact that replacing the inductor with
a zero ohm resistor can making the PLL work again. If indeed this is a
frequency response problem, it is hard for me to believe a RC filter with R
close to zero can have better response than a LC combo (sure you can talk
about the Q but replacing the inductor with a higher ESR one or with some
series resistor can instantly verify the problem).
I am with Istvan on this one, at least you should check the DC level of the
power going into the PLLVDD with the zero ohm and inductor. Sometimes these
low voltage PLL has a very limited range of operation and the IR drop on the
inductor due to its ESR may just be enough to make it "not working" or
whatever it means.
If however, by inserting a series resistor on your inductor and all the
sudden the PLL is alive again, you will need to do a complete power noise
frequency to jitter response. That will be another long and lengthy
discussion.
-----Original Message-----
From: steve weir
To: istvan.novak@xxxxxxxxxxxxxxxx; leeritchey@xxxxxxxxxxxxx; zhangkun 29902
Cc: a.ingraham@xxxxxxxx; si-list@xxxxxxxxxxxxx
Sent: 8/29/2004 8:06 PM
Subject: [SI-LIST] Re: Decoupling for PLL
All, while Lee makes a good point that a well designed power system is a
critical system design requirement, my experience is closer to Istvan's
on
this. Mfg's who give us scant hard information on power system
requirements generally do even worse when it comes to PLLs. I would
like
to paraphrase Lee's comments as holding Vcc rail noise as: "Holding Vcc
noise to a 'low level' up to a few MHz obviates the need for separate
low-frequency power filtering to PLLs". A well behaved main power
supply
up past the first few harmonics of the VRM switching voltage should
eliminate the need for a low frequency cut-off decoupling filter.
However,
it won't necessarily eliminate the need for it.
A point that I think is worth mentioning is SSO. When the PLL power pin
is
tied directly tot he planes, the PLL power pin becomes part of the
signal
image return path, unnecessarily imposing voltage drops across the PLL
internal power distribution to SSO induced noise currents. Whether a
given
PLL can tolerate those currents or not, is chip design specific. A
decoupling filter with a high series impedance blocks those currents.
But
now, if we have a "suitably quiet" Vcc up into the low MHz, the filter
cut-off frequency can be similarly high, and the design can be very
compact.
So, how much noise at what frequency can a given PLL tolerate? Wouldn't
it
be nice if the chip mfgs told us?
Steve.
At 06:26 PM 8/29/2004 -0400, Istvan NOVAK wrote:
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