[SI-LIST] IEEE1394/Ethernet Routing Guidelines
- From: Randolph Voorhies <voorhies@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 30 May 2007 11:59:12 -0700
Hi Everyone,
I'm brand new not just to this list, but to the world of PCB production in
general. I'm currently a masters student at USC in robotics and have been
producing some relatively simple PCBs for the past few months using Eagle. I'm
now working on a fairly complex project that involves creating a custom
baseboard for an XTX module (xtx-standard.org). My formal training is in
digital electronics, computer architecture, and computer science, so when it
comes to signal integrity I'm pretty much at a loss. Does anyone know where to
find specific routing guidlines for differential pair lines such as firewire
and ethernet? I have read all sorts of conflicting advice (differential
impedence is crucial vs. differential impedence couldn't matter less, etc..),
and have had a very difficult time finding exact numbers for trace
spacing/individual trace impedence and so on. If anyone with experience has any
advice that has worked for them it would be very very very much appreciated.
Thanks so much,
Rand Voorhies
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- From: Bill Owsley
- [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
- From: steve weir
- [SI-LIST] Arguments against Thevenin bias/termination for ddr2 Vtt
- From: agathon
- [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt
- From: agathon
- [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt
- From: steve weir
- [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt
- From: agathon