[SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines

  • From: Bill Owsley <wdowsley@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Fri, 1 Jun 2007 09:24:03 -0700 (PDT)

I used one of those really fast TDR pulse generators into one end of both 
traces.  They are a pair.  And then using a similarly fast o'scope at the other 
end and two channels, looked at the results.  Note, there are many ways to 
really screw this up - I've found several.  However, you'll have to find your 
own.  
  ps. It's really fun looking for femtoseconds, and if you squint just right...
   
  And so I learned to watch the layout designers and thus came to believe that 
yes indeed they could do what they claimed to have done.  They make my job so 
much easier - thanks to all the layout designers here.
   
  
Craig Twardy <ctwardy@xxxxxxxxxx> wrote:
  Lee and others.

Matching the pair length to 1mil works out to about 0.16 psec skew.
(if I did the math right (FR4))
How would one measure the design to verify this length matching was
achieved?=20
Not sure I could measure this in the lab with the scopes I have.
(at least not without spending days calibrating the setup)

Perhaps there are other ways to get this resolution.

Craig=20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: May 31, 2007 3:03 PM
To: leeritchey@xxxxxxxxxxxxx
Cc: Ravinder.Ajmani@xxxxxxxxxxxxxx; wdowsley@xxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines

Lee, well FREE is the caveat, isn't it?=20

Intuitively ( because I have never tried to run a controlled experiment
to prove or disprove this ) I believe there is a match requirement,
maybe 50 mils, maybe 25 mils that costs just as much router time as
whatever the tool resolution is.=20

Best Regards,


Steve.

Lee Ritchey wrote:
> Ay! But ultra tight matching is not free. It requires hand routing=20
> and that takes time, which always costs money. If the matching spec=20
> is done right, the autorouter can do the job and that does save time.
>
>
> =20
>> [Original Message]
>> From: steve weir 
>> To: 
>> Cc: Ravinder.Ajmani@xxxxxxxxxxxxxx ;
>> =20
> ; 
> =20
>> Date: 5/31/2007 10:25:11 AM
>> Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
>>
>> Lee, Ravinder, et-al,
>>
>> Sure you can't get anything remotely close to 1mil matched true=20
>> electrical length on the PCB itself, never mind what the package
does.
>> The variations in eR over the signal path see to that. But telling=20
>> the tool to effectively exactly match the physical length, simply=20
>> reduces an additional error term. At least on paper that is a good=20
>> thing, IF it is free. From the standpoint of entering constraints in

>> the tool it might seem to be. But there are some potential hidden=20
>> gotcha's, like the coupling between adjacent segments of meanders,=20
>> and excessive real-estate for meanders.
>>
>> Best Regards,
>>
>>
>>
>> Steve.
>>
>>
>> Lee Ritchey wrote:
>> =20
>>> Requiring length matching to 1 mil is excessively restrictive and=20
>>> not attainable due to unknown lengths in IC packages and on die
lengths.
>>> =20
> The
> =20
>>> fact that a layout person can do this on the PCB isn't a reason to
>>> =20
> impose
> =20
>>> such a restrictive matching rule. I'd be willing to bet that the=20
>>> real length matching on the PCB is not the claimed 1 mil. That's=20
>>> just what
>>> =20
> the
> =20
>>> tool reports.
>>>
>>>
>>> =20
>>> =20
>>>> [Original Message]
>>>> From: 
>>>> To: 
>>>> Cc: 
>>>> Date: 5/31/2007 9:13:25 AM
>>>> Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
>>>>
>>>> Bill,
>>>> While I agree with almost all of your recommendations, I do not
>>>> =20
>>>> =20
>>> understand
>>> =20
>>> =20
>>>> the need to match the length of differential pairs to within 1 mil.

>>>> =20
> Will
> =20
>>>> you please give your reasoning for this.
>>>>
>>>> Thanks.
>>>>
>>>> Regards, Ravinder
>>>> Server PCB Development
>>>> Hitachi Global Storage Technologies
>>>>
>>>>
>>>> Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
>>>>
>>>>
>>>>
>>>> Bill Owsley 
>>>> Sent by: si-list-bounce@xxxxxxxxxxxxx
>>>> 05/30/2007 08:13 PM
>>>> Please respond to
>>>> wdowsley@xxxxxxxxx
>>>>
>>>>
>>>> To
>>>> Sam.Charles@xxxxxxxx, jeff.loyer@xxxxxxxxx cc=20
>>>> si-list@xxxxxxxxxxxxx, si-list-bounce@xxxxxxxxxxxxx,=20
>>>> weirsi@xxxxxxxxxx Subject [SI-LIST] Re: IEEE1394/Ethernet Routing=20
>>>> Guidelines
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> I went below to check what Mr.Voorhies asked for;
>>>> "...have had a very difficult time finding exact numbers for=20
>>>> trace spacing/individual trace impedence and so on."
>>>> =20
>>>> And now I don't find in any of the suggestions (or in Mr.Voorhies
>>>> =20
> note)
> =20
>>>> anything about copper weight, dielectric constant at what=20
>>>> frequency,
>>>> =20
>>>> =20
>>> trace
>>> =20
>>> =20
>>>> width, distance above or between reference planes, length matching,
>>>> =20
>>>> =20
>>> number
>>> =20
>>> =20
>>>> of vias across how many layers, crosstalk coupling factor and it's
>>>> =20
> effect
> =20
>>>> on even/odd mode impedance, pre-emphasis to compensate for longer
>>>> =20
> lengths
> =20
>>>> at higher frequencies, various "cute tricks" to emulate=20
>>>> differential signals (one I really like, nearly eliminates most of=20
>>>> the above), differential drivers or complementary drivers or=20
>>>> current steering
>>>> =20
>>>> =20
>>> drivers,
>>> =20
>>> =20
>>>> differential to common mode conversion factor, terminations,
>>>> =20
> decoupling,
> =20
>>>> and so on. All the books/sources referenced have all the=20
>>>> conflicting information that Mr. Voorhies has already discovered.
>>>> For us, immersed in the culture (or lack of it on my part) the
>>>> =20
> references
> =20
>>>> are like preaching to the choir, we nod our collective heads in
>>>> =20
> agreement
> =20
>>>> that those are indeed good sources and Mr. Voorhies says to=20
>>>> himself,
>>>> =20
> Hey
> =20
>>>> =20
>>>> =20
>>> I
>>> =20
>>> =20
>>>> can catch lightning in a jar, but I still don't WTF they just said,
>>>> =20
> thus
> =20
>>>> the reason for his request. Everyday we work with digit heads,=20
>>>> okay, digital guys, who connect to the dots and then look to the SI

>>>> and EMC
>>>> =20
>>>> =20
>>> guys
>>> =20
>>> =20
>>>> to make the board work. ps. we work well together cuz the only=20
>>>> dots I connect are in my granddaughters coloring book.
>>>> So given the dearth of details here's one answer (of many) he can
>>>> =20
> use;
> =20
>>>> 50 ohm surface traces (no vias), spaced 5 times the distance to=20
>>>> the reference plane, no breaks in the plane below the traces,=20
>>>> matched
>>>> =20
> lengths
> =20
>>>> to within 1 mil. (my layout guys can do that in about 30 seconds=20
>>>> all
>>>> =20
> day,
> =20
>>>> another "cute trick"), and all added parts are absolute mirrow
>>>> =20
> symmetric
> =20
>>>> (the parts might need vias).=20
>>>> =20
>>>> =20
>>>> =20
>>>> =20
>>>> =20
>>>> =20
>>>> =20
>>>> Sam.Charles@xxxxxxxx wrote:
>>>> I second that.
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> "Loyer, Jeff"=20
>>>>
>>>> Sent by: To
>>>> si-list-bounce@xxxxxxxxxxxxx
>>>> cc
>>>>
>>>> 05/30/2007 02:24 PM Subject
>>>> [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
>>>>
>>>> Please respond to
>>>> jeff.loyer@xxxxxxxxx
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> THANK YOU!!!
>>>>
>>>> A response absent of sarcasm and/or scorn, and with some useful=20
>>>> information. A pleasant change from the recent postings on the
forum.
>>>>
>>>> Thanks Steve,
>>>>
>>>> Jeff Loyer
>>>>
>>>> -----Original Message-----
>>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>> =20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> =20
>>>> On Behalf Of steve weir
>>>> Sent: Wednesday, May 30, 2007 1:39 PM
>>>> To: voorhies@xxxxxxx
>>>> Cc: si-list@xxxxxxxxxxxxx
>>>> Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
>>>>
>>>> Randolph, I suggest any of the following four books would be=20
>>>> helpful to y=3D3D
>>>> ou:
>>>>
>>>> Signal Integrity Simplified, Bogatin High Speed Signal Propagation,

>>>> Johnson and Graham Digital Techniques for High Speed Design,=20
>>>> Granberg Right the First Time Vol II, Ritchey
>>>>
>>>> Lee Ritchey self publishes so if you want Right the First Time you=20
>>>> will =3D3D
>>>>
>>>> need to go to www.speedingedge.com. Your alternative is to rely on=20
>>>> PHY=3D3D20 manufacturer guidelines.
>>>>
>>>> The basic guide that I can offer you is this:
>>>>
>>>> * Loosely coupled pairs are easier to manage than tightly=20
>>>> coupled=3D3D20 pairs. If you don't specifically need tight coupling =

>>>> for density=3D3D20 reasons, you will be less likely to go wrong =
with=20
>>>> loosely coupled
>>>> =20
> pairs.
> =20
>>>> =3D3D
>>>>
>>>>
>>>> * The crude approximation for a loosely coupled pair is Zodd =
=3D3D3D=20
>>>> 2*Zeven.=3D3D =3D3D20 Ie two loosely coupled 50 ohm traces will =
have=20
>>>> about a 100ohm odd mode=3D3D20 impedance.=3D3D20
>>>>
>>>> * Maintaining a uniform impedance and matched electrical length=20
>>>> will do=3D3D20 much to get you were you need to go. If you are a =
tiny

>>>> bit sloppy, it=3D3D20 shouldn't matter for a student project. Your=20
>>>> project doesn't have =3D to=3D3D20 pass FCC part B, and it is =
unlikely=20
>>>> that you have to support =3D maximal=3D3D20 length links.
>>>>
>>>> Eric Bogatin's book has some impedance nomographs. However, there=20
>>>> are a =3D3D
>>>>
>>>> number of free calculators around some better than others. Google=20
>>>> for=3D3D20 impedance calculator and take your pick.=3D3D20
>>>>
>>>> Good luck.
>>>>
>>>> Steve.
>>>>
>>>>
>>>>
>>>> Randolph Voorhies wrote:
>>>> =20
>>>> =20
>>>>> Hi Everyone,
>>>>> I'm brand new not just to this list, but to the world of PCB
>>>>> =20
>>>>> =20
>>>> product=3D3D
>>>> ion in general. I'm currently a masters student at USC in robotics=20
>>>> and h=3D3D ave been producing some relatively simple PCBs for the=20
>>>> past few months us=3D3D ing Eagle. I'm now working on a fairly=20
>>>> complex project that involves crea=3D3D ting a custom baseboard for =

>>>> an XTX module (xtx-standard.org). My formal =3D3D training is in=20
>>>> digital electronics, computer architecture, and computer s=3D3D=20
>>>> cience, so when it comes to signal integrity I'm pretty much at a
loss.
>>>> =3D3D
>>>> Does anyone know where to find specific routing guidlines for=20
>>>> differentia=3D3D l pair lines such as firewire and ethernet? I have =

>>>> read all sorts of conf=3D3D licting advice (differential impedence =
is

>>>> crucial vs. differential impede=3D3D nce couldn't matter less,=20
>>>> etc..), and have had a very difficult time find=3D3D ing exact=20
>>>> numbers for trace spacing/individual trace impedence and so =
on.=3D3D=20
>>>> If anyone with experience has any advice that has worked for them=20
>>>> it wou=3D3D ld be very very very much appreciated.
>>>> =20
>>>> =20
>>>>> Thanks so much,
>>>>> Rand Voorhies
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