[SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines

Bill-
 

You are asking the SI list to give you some specific design rules to follow
to help you meet your design spec. I think the advice you are getting is
basically that the precise design rule of what line width, what spacing,
what dielectric thickness, what copper thickness to use, to achieve a
particular target single ended or differential impedance, depends on your
application and the tradeoffs you want between total board thickness,
manufacturing design rules, interconnect density, routing constraints,
design margin and cost. 

 

When you ask a general question, the information you get from this email
group is about the process to use to find your answer, not the specific
answers. 

 

What you are hearing from this group is that you first need to understand
the principles behind the question you are asking, so you know if it's even
the right question, and what to do with the answer when you get it. 

 

Next, you need the right tools to translate general design guidelines into
specific design rules. 

 

If you want a narrow design margin for a target impedance, and not over
design your products, you need an accurate analysis tool, like a 2D field
solver.

 

If all you need is 10-20% accuracy, feel free to use the tables and charts
you see in various books. 

 

You can use a free online calculator that is accurate to between 3-10%, or
rent a 2D field solver, for about $20 an hour from the Polar Instruments web
site that is accurate to 1%.

 

When you see folks on this list saying, "do your homework", I think we are
referring to understand the essential principles- check some of the books or
classes or freely available feature articles already posted on various web
sites, learn to use the tools already available to you, and learn to apply
the principles and tools to your applications. 

 

If you don't want to do your homework so you can solve your own problems,
which is perfectly ok, there are a number of SI-list regulars who would be
delighted to consult for you. 

 

--eric

 

 

 

 

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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Bill Owsley
Sent: Wednesday, May 30, 2007 10:14 PM
To: Sam.Charles@xxxxxxxx; jeff.loyer@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx; weirsi@xxxxxxxxxx
Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines

 

I went below to check what Mr.Voorhies asked for;

  "...have had a very difficult time finding exact numbers for trace
spacing/individual trace impedence and so on."

   

  And now I don't find in any of the suggestions (or in Mr.Voorhies note)
anything about copper weight, dielectric constant at what frequency, trace
width, distance above or between reference planes, length matching, number
of vias across how many layers, crosstalk coupling factor and it's effect on
even/odd mode impedance, pre-emphasis to compensate for longer lengths at
higher frequencies, various "cute tricks" to emulate differential signals
(one I really like, nearly eliminates most of the above), differential
drivers or complementary drivers or current steering drivers, differential
to common mode conversion factor, terminations, decoupling, and so on.  All
the books/sources referenced have all the conflicting information that Mr.
Voorhies has already discovered.  

For us, immersed in the culture (or lack of it on my part) the references
are like preaching to the choir, we nod our collective heads in agreement
that those are indeed good sources and Mr. Voorhies says to himself, Hey I
can catch lightning in a jar, but I still don't WTF they just said, thus the
reason for his request.  Everyday we work with digit heads, okay, digital
guys, who connect to the dots and then look to the SI and EMC guys to make
the board work.  ps. we work well together cuz the only dots I connect are
in my granddaughters coloring book.

  So given the dearth of details here's one answer (of many) he can use;

  50 ohm surface traces (no vias), spaced 5 times the distance to the
reference plane, no breaks in the plane below the traces, matched lengths to
within 1 mil. (my layout guys can do that in about 30 seconds all day,
another "cute trick"), and all added parts are absolute mirrow symmetric
(the parts might need vias).  

   

   

   

   

   

   

 



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