Posts for si-list, 05-2007

Browse: Last Month: 04-2007 Main Archive Page Next Month: 06-2007

» [SI-LIST] Have anybody applied EBG in his(her) design? -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: Tie-Bars? Industry Standard? -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: FW: diff pair routing at 10gig -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Tie-Bars? Industry Standard? -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] FW: diff pair routing at 10gig -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Signal integrate 1.5GHz -
» [SI-LIST] Signal integrate 1.5GHz -
» [SI-LIST] Signal integrate 1.5GHz -
» [SI-LIST] Signal integrate 1.5GHz -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: High Speed Routing -
» [SI-LIST] Re: High Speed Routing -
» [SI-LIST] Re: FER Test Vs BER Test in SATA -
» [SI-LIST] Re: FER Test Vs BER Test in SATA -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Re: High Speed Routing -
» [SI-LIST] Re: High Speed Routing -
» [SI-LIST] Re: High Speed Routing -
» [SI-LIST] IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Re: High Speed Routing -
» [SI-LIST] Re: Half OT: large PCB at -40C -
» [SI-LIST] High Speed Routing -
» [SI-LIST] diff pair routing at 10gig -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] Arguments against Thevenin bias/termination for ddr2 Vtt -
» [SI-LIST] System Level ESD Engineer Position at Texas Instruments -
» [SI-LIST] Re: Oscilloscope showing 50Hz signal -
» [SI-LIST] Half OT: large PCB at -40C -
» [SI-LIST] Re: Gen2 PCIe packaging interconnect questions -
» [SI-LIST] Gen2 PCIe packaging interconnect questions -
» [SI-LIST] Re: Crystal osciiator not oscillating -
» [SI-LIST] Re: Fwd: Re: Re: Crystal osciiator not oscillating -
» [SI-LIST] FER Test Vs BER Test in SATA -
» [SI-LIST] Re: Fwd: Re: Re: Crystal osciiator not oscillating -
» [SI-LIST] Re: GbE LLC/SNAP -
» [SI-LIST] Re: Oscilloscope showing 50Hz signal -
» [SI-LIST] Re: From spectrum of i(t) to spectrum of d(i(t))/dt -
» [SI-LIST] Re: DDR2 SI -
» [SI-LIST] AC97 specfications -
» [SI-LIST] Oscilloscope showing 50Hz signal -
» [SI-LIST] Re: Return loss measurement - odd result - why? -
» [SI-LIST] Michael W Wielebski/Mequon/RA/Rockwell is out of the office. -
» [SI-LIST] Fwd: Re: Re: Crystal osciiator not oscillating -
» [SI-LIST] Re: Crystal osciiator not oscillating -
» [SI-LIST] Re: DDR2 SI -
» [SI-LIST] Re: DDR2 SI -
» [SI-LIST] Re: DDR2 SI -
» [SI-LIST] GbE LLC/SNAP -
» [SI-LIST] Re: Need more insight on usage of a connector -
» [SI-LIST] Re: Need more insight on usage of a connector -
» [SI-LIST] Need more insight on usage of a connector -
» [SI-LIST] Michael W Wielebski/Mequon/RA/Rockwell is out of the office. -
» [SI-LIST] Re: Crystal osciiator not oscillating -
» [SI-LIST] Re: Power Distribution Modeling Techniques -
» [SI-LIST] DDR2 SI -
» [SI-LIST] Re: DDR2 Signal Probing on SODIMM -
» [SI-LIST] Re: DDR2 Signal Probing on SODIMM -
» [SI-LIST] Re: DDR2 Signal Probing on SODIMM -
» [SI-LIST] Re: DDR2 Signal Probing on SODIMM -
» [SI-LIST] Re: Power Distribution Modeling Techniques -
» [SI-LIST] Re: Power Distribution Modeling Techniques -
» [SI-LIST] Power Distribution Modeling Techniques -
» [SI-LIST] Crystal osciiator not oscillating -
» [SI-LIST] DDR2 Signal Probing on SODIMM -
» [SI-LIST] Technician needed at Marvell -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: From spectrum of i(t) to spectrum of d(i(t))/dt -
» [SI-LIST] Re: From spectrum of i(t) to spectrum of d(i(t))/dt -
» [SI-LIST] Re: From spectrum of i(t) to spectrum of d(i(t))/dt -
» [SI-LIST] Re: From spectrum of i(t) to spectrum of d(i(t))/dt -
» [SI-LIST] Re: From spectrum of i(t) to spectrum of d(i(t))/dt -
» [SI-LIST] Re: Matching differential traces -
» [SI-LIST] Re: Matching differential traces -
» [SI-LIST] Re: Matching differential traces -
» [SI-LIST] Re: Diff pair length matching -
» [SI-LIST] Re: Matching differential traces -
» [SI-LIST] Re: Diff pair length matching -
» [SI-LIST] Diff pair length matching -
» [SI-LIST] Matching differential traces -
» [SI-LIST] Re: Transfer impedance -
» [SI-LIST] Re: Return loss measurement - odd result - why? -
» [SI-LIST] Transfer impedance -
» [SI-LIST] Re: Return loss measurement - odd result - why? -
» [SI-LIST] Re: Return loss measurement - odd result - why? -
» [SI-LIST] Return loss measurement - odd result - why? -
» [SI-LIST] Re: ESD, shoes, and hospitals... -
» [SI-LIST] Board Design Lead--San Jose, CA -
» [SI-LIST] FW: TLM: Laplace and discrete difference equations - Thanks for the responses. -
» [SI-LIST] From spectrum of i(t) to spectrum of d(i(t))/dt -
» [SI-LIST] Re: TLM: Laplace and discrete difference equations -
» [SI-LIST] Re: TLM: Laplace and discrete difference equations -
» [SI-LIST] Re: TLM: Laplace and discrete difference equations -
» [SI-LIST] Re: TLM: Laplace and discrete difference equations -
» [SI-LIST] TLM: Laplace and discrete difference equations -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Wolfgang Maichen/USW/Teradyne is out of the office. -
» [SI-LIST] SI Openning at Marvell -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Re: his niagara -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Re: ESD, shoes, and hospitals... -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Re: MATLAB for SI -
» [SI-LIST] Re: ESD, shoes, and hospitals... -
» [SI-LIST] MATLAB for SI -
» [SI-LIST] Re: ESD, shoes, and hospitals... -
» [SI-LIST] ESD, shoes, and hospitals... -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: 2.5D and 3D Solvers -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: 2.5D and 3D Solvers -
» [SI-LIST] Re: 2.5D and 3D Solvers -
» [SI-LIST] FW: [IBIS] About Fork in The Package Model -
» [SI-LIST] 2.5D and 3D Solvers -
» [SI-LIST] Re: Stimulus dilemma for pwr/gnd model -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] Re: Rise time bandwidth relation -
» [SI-LIST] placement of added capacitors during troubleshooting -
» [SI-LIST] Re: SSO SSTL Vs LVTTL -
» [SI-LIST] Re: Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Re: Fw: Re: Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Re: Fw: Re: Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Re: Fw: Re: Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Fw: Re: Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Re: Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Re: Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Re: Understanding S-Parameters -
» [SI-LIST] Re: SSO SSTL Vs LVTTL -
» [SI-LIST] Re: SSO SSTL Vs LVTTL -
» [SI-LIST] Re: TFT display modules with _min_ dot clock frequency spec -
» [SI-LIST] Re: TFT display modules with _min_ dot clock frequency spec -
» [SI-LIST] Re: SSTl2 SSO simulation set-up -
» [SI-LIST] Inexpensive TDR for short/open localizing on a PCB -
» [SI-LIST] Re: Understanding S-Parameters -
» [SI-LIST] Re: Understanding S-Parameters -
» [SI-LIST] Re: Understanding S-Parameters -
» [SI-LIST] Understanding S-Parameters -
» [SI-LIST] don't lump that C (new subject) -
» [SI-LIST] Re: TFT display modules with _min_ dot clock frequency spec -
» [SI-LIST] SSTl2 SSO simulation set-up -
» [SI-LIST] Re: TFT display modules with _min_ dot clock frequency spec -
» [SI-LIST] TFT display modules with _min_ dot clock frequency spec -
» [SI-LIST] Join the Anatrim revolution -
» [SI-LIST] Possible Opportunity with Cisco: Signal Integrity Manager -