[SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Steve Weir" <weirsi@xxxxxxxxxx>
- Date: Thu, 31 May 2007 11:50:57 -0700
Ay! But ultra tight matching is not free. It requires hand routing and
that takes time, which always costs money. If the matching spec is done
right, the autorouter can do the job and that does save time.
> [Original Message]
> From: steve weir <weirsi@xxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>
> Cc: Ravinder.Ajmani@xxxxxxxxxxxxxx <Ravinder.Ajmani@xxxxxxxxxxxxxx>;
<wdowsley@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 5/31/2007 10:25:11 AM
> Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
>
> Lee, Ravinder, et-al,
>
> Sure you can't get anything remotely close to 1mil matched true
> electrical length on the PCB itself, never mind what the package does.
> The variations in eR over the signal path see to that. But telling the
> tool to effectively exactly match the physical length, simply reduces an
> additional error term. At least on paper that is a good thing, IF it is
> free. From the standpoint of entering constraints in the tool it might
> seem to be. But there are some potential hidden gotcha's, like the
> coupling between adjacent segments of meanders, and excessive
> real-estate for meanders.
>
> Best Regards,
>
>
>
> Steve.
>
>
> Lee Ritchey wrote:
> > Requiring length matching to 1 mil is excessively restrictive and not
> > attainable due to unknown lengths in IC packages and on die lengths.
The
> > fact that a layout person can do this on the PCB isn't a reason to
impose
> > such a restrictive matching rule. I'd be willing to bet that the real
> > length matching on the PCB is not the claimed 1 mil. That's just what
the
> > tool reports.
> >
> >
> >
> >> [Original Message]
> >> From: <Ravinder.Ajmani@xxxxxxxxxxxxxx>
> >> To: <wdowsley@xxxxxxxxx>
> >> Cc: <si-list@xxxxxxxxxxxxx>
> >> Date: 5/31/2007 9:13:25 AM
> >> Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
> >>
> >> Bill,
> >> While I agree with almost all of your recommendations, I do not
> >>
> > understand
> >
> >> the need to match the length of differential pairs to within 1 mil.
Will
> >> you please give your reasoning for this.
> >>
> >> Thanks.
> >>
> >> Regards, Ravinder
> >> Server PCB Development
> >> Hitachi Global Storage Technologies
> >>
> >>
> >> Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
> >>
> >>
> >>
> >> Bill Owsley <wdowsley@xxxxxxxxx>
> >> Sent by: si-list-bounce@xxxxxxxxxxxxx
> >> 05/30/2007 08:13 PM
> >> Please respond to
> >> wdowsley@xxxxxxxxx
> >>
> >>
> >> To
> >> Sam.Charles@xxxxxxxx, jeff.loyer@xxxxxxxxx
> >> cc
> >> si-list@xxxxxxxxxxxxx, si-list-bounce@xxxxxxxxxxxxx, weirsi@xxxxxxxxxx
> >> Subject
> >> [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
> >>
> >>
> >>
> >>
> >>
> >>
> >> I went below to check what Mr.Voorhies asked for;
> >> "...have had a very difficult time finding exact numbers for trace
> >> spacing/individual trace impedence and so on."
> >>
> >> And now I don't find in any of the suggestions (or in Mr.Voorhies
note)
> >> anything about copper weight, dielectric constant at what frequency,
> >>
> > trace
> >
> >> width, distance above or between reference planes, length matching,
> >>
> > number
> >
> >> of vias across how many layers, crosstalk coupling factor and it's
effect
> >> on even/odd mode impedance, pre-emphasis to compensate for longer
lengths
> >> at higher frequencies, various "cute tricks" to emulate differential
> >> signals (one I really like, nearly eliminates most of the above),
> >> differential drivers or complementary drivers or current steering
> >>
> > drivers,
> >
> >> differential to common mode conversion factor, terminations,
decoupling,
> >> and so on. All the books/sources referenced have all the conflicting
> >> information that Mr. Voorhies has already discovered.
> >> For us, immersed in the culture (or lack of it on my part) the
references
> >> are like preaching to the choir, we nod our collective heads in
agreement
> >> that those are indeed good sources and Mr. Voorhies says to himself,
Hey
> >>
> > I
> >
> >> can catch lightning in a jar, but I still don't WTF they just said,
thus
> >> the reason for his request. Everyday we work with digit heads, okay,
> >> digital guys, who connect to the dots and then look to the SI and EMC
> >>
> > guys
> >
> >> to make the board work. ps. we work well together cuz the only dots I
> >> connect are in my granddaughters coloring book.
> >> So given the dearth of details here's one answer (of many) he can
use;
> >> 50 ohm surface traces (no vias), spaced 5 times the distance to the
> >> reference plane, no breaks in the plane below the traces, matched
lengths
> >> to within 1 mil. (my layout guys can do that in about 30 seconds all
day,
> >> another "cute trick"), and all added parts are absolute mirrow
symmetric
> >> (the parts might need vias).
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >> Sam.Charles@xxxxxxxx wrote:
> >> I second that.
> >>
> >>
> >>
> >>
> >>
> >> "Loyer, Jeff"
> >>
> >> Sent by: To
> >> si-list-bounce@xxxxxxxxxxxxx
> >> cc
> >>
> >> 05/30/2007 02:24 PM Subject
> >> [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
> >>
> >> Please respond to
> >> jeff.loyer@xxxxxxxxx
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >> THANK YOU!!!
> >>
> >> A response absent of sarcasm and/or scorn, and with some useful
> >> information. A pleasant change from the recent postings on the forum.
> >>
> >> Thanks Steve,
> >>
> >> Jeff Loyer
> >>
> >> -----Original Message-----
> >> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> >> On Behalf Of steve weir
> >> Sent: Wednesday, May 30, 2007 1:39 PM
> >> To: voorhies@xxxxxxx
> >> Cc: si-list@xxxxxxxxxxxxx
> >> Subject: [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines
> >>
> >> Randolph, I suggest any of the following four books would be helpful to
> >> y=3D
> >> ou:
> >>
> >> Signal Integrity Simplified, Bogatin
> >> High Speed Signal Propagation, Johnson and Graham
> >> Digital Techniques for High Speed Design, Granberg
> >> Right the First Time Vol II, Ritchey
> >>
> >> Lee Ritchey self publishes so if you want Right the First Time you will
> >> =3D
> >>
> >> need to go to www.speedingedge.com. Your alternative is to rely on
> >> PHY=3D20
> >> manufacturer guidelines.
> >>
> >> The basic guide that I can offer you is this:
> >>
> >> * Loosely coupled pairs are easier to manage than tightly coupled=3D20
> >> pairs. If you don't specifically need tight coupling for density=3D20
> >> reasons, you will be less likely to go wrong with loosely coupled
pairs.
> >> =3D
> >>
> >>
> >> * The crude approximation for a loosely coupled pair is Zodd =3D3D
> >> 2*Zeven.=3D
> >> =3D20
> >> Ie two loosely coupled 50 ohm traces will have about a 100ohm odd
> >> mode=3D20
> >> impedance.=3D20
> >>
> >> * Maintaining a uniform impedance and matched electrical length will
> >> do=3D20
> >> much to get you were you need to go. If you are a tiny bit sloppy,
> >> it=3D20
> >> shouldn't matter for a student project. Your project doesn't have =
> >> to=3D20
> >> pass FCC part B, and it is unlikely that you have to support =
> >> maximal=3D20
> >> length links.
> >>
> >> Eric Bogatin's book has some impedance nomographs. However, there are a
> >> =3D
> >>
> >> number of free calculators around some better than others. Google
> >> for=3D20
> >> impedance calculator and take your pick.=3D20
> >>
> >> Good luck.
> >>
> >> Steve.
> >>
> >>
> >>
> >> Randolph Voorhies wrote:
> >>
> >>> Hi Everyone,
> >>> I'm brand new not just to this list, but to the world of PCB
> >>>
> >> product=3D
> >> ion in general. I'm currently a masters student at USC in robotics and
> >> h=3D
> >> ave been producing some relatively simple PCBs for the past few months
> >> us=3D
> >> ing Eagle. I'm now working on a fairly complex project that involves
> >> crea=3D
> >> ting a custom baseboard for an XTX module (xtx-standard.org). My formal
> >> =3D
> >> training is in digital electronics, computer architecture, and computer
> >> s=3D
> >> cience, so when it comes to signal integrity I'm pretty much at a loss.
> >> =3D
> >> Does anyone know where to find specific routing guidlines for
> >> differentia=3D
> >> l pair lines such as firewire and ethernet? I have read all sorts of
> >> conf=3D
> >> licting advice (differential impedence is crucial vs. differential
> >> impede=3D
> >> nce couldn't matter less, etc..), and have had a very difficult time
> >> find=3D
> >> ing exact numbers for trace spacing/individual trace impedence and so
> >> on.=3D
> >> If anyone with experience has any advice that has worked for them it
> >> wou=3D
> >> ld be very very very much appreciated.
> >>
> >>> Thanks so much,
> >>> Rand Voorhies
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