[SI-LIST] Re: IBIS Model Quality (or lack thereof)
- From: "Jeremy Plunkett" <jeremy@xxxxxxxxxxxxxxx>
- To: twester@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 26 Mar 2002 16:39:59 -0800
Hi Todd,
the test loads you describe below are very similar to ones that I =
typically use. There is no single test load that is appropriate for all =
buffers; in general I use a test load that is the simplest possible =
representation of the actual load the buffer will drive in service. For =
a terminated bus this would be a transmission line at the nominal trace =
impedance with the nominal termination at the endpoint(s) and a typical =
receiver load capacitance, or in the simplest case a resistor equal to =
the line impedance, connected to the termination voltage (useful for =
measuring the drive strength and output waveforms only, no reflection =
effects). For an unterminated or series terminated bus, a test load =
with perfect termination to 1/2 VDD is not relevant, since this is a =
case that does not occur on the bus in service. It may correlate fine, =
but even if it doesn't, that isn't necessarily a mark against the model. =
For these busses the best test load is the 2nd one you describe with no =
termination on the line and a capacitance at the receiver.
Jeremy
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Todd Westerhoff
Sent: Tuesday, March 26, 2002 2:55 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS Model Quality (or lack thereof)
Thanks everyone, for your contributions to this thread so far. By way =
of
summary, we've heard from the following semiconductor companies:
- Intel
- Fairchild
- Serverworks
(if I left anyone out, my apologies)
... and I'll vouch for both Intel and Micron myself, both in terms of =
model
quality and support.
It is my strong suspicion that precious few IBIS models are validated in =
any
meaningful way before they are shipped to the customer. A few of your =
have
expressed hopes for the IBIS model quality committee that has just =
gotten
started, I share your hopes and enthusiasm for the effort.
A number of you have outlined some of the testing processes you use, and =
I'd
like to suggest that we explore that subject a bit more. We've spent a =
LOT
of time here lately correlating IBIS models to their HSpice =
counterparts.
We're currently using two "standard" text fixtures to compare =
IBIS/HSpice
models:
* I/O buffer connected to VDDQ/2 through 50 ohms
* I/O buffer connected to 0.5ns, 50ohm tline, 5pf to GND at tline end
The theory is that the first test fixture compares rising/falling edge
characteristics and buffer strength, while the second test models the
driver's response to a reflected wave (primarily the value of C_Comp). =
If
you get the HSpice/IBIS buffers to agree across these two tests, chances =
are
the rest of the puzzle falls into place, provided you agree on things =
like
pin parasitics and switching thresholds.
So, I'm curious - for those of you who test IBIS models against any kind =
of
reference (HSpice or measurement) - what kinds of test loads are you =
using,
and what are you looking for?
As always, all input (on and off the list) is greatly appreciated.
Todd.
Todd Westerhoff
Signal Integrity Engineer
Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@xxxxxxxxxxx - ph: 978-671-5084
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
"I=92m starting With the man in the mirror
I=92m asking him to change his ways
And no message could have been any clearer
If you wanna make the world a better place
Take a look at yourself, and then make a change"
- "Man in the Mirror", Michael Jackson
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