[SI-LIST] Re: design of on-chip PDN
- From: Iliya Zamek <i_zamek@xxxxxxxxx>
- To: Istvan Novak <istvan.novak@xxxxxxx>, Siming Pan <pansiming86@xxxxxxxxx>
- Date: Mon, 1 Nov 2010 22:40:23 -0700 (PDT)
I agree with Istvan and Cosmin comments.
Adding to the analysis the fact that SERDES PDN’ resonance frequency in orders
higher then Core PDN’ resonance frequency, we might get some more insights into
the problem.
1. Really, when both PDNs are separate, current variations inside PDNs cause
voltage variations which, next in tern, cause timing variations in Core and
SERDES. So, timing of whole system of Core-SERDES might be big, but Core and
SERDES timing are relatively independent of each other. On-chip decoupling in
Core and SERDES PDNs helps to manage these variations.
2. When Power networks are connected on-chip, suppose with negligible
inductance, it improves situation for the SERDES significantly, by reducing
both, noise due to the SERDES current variations and noise coming from PCB.
SERDES will have, together with the Core, huge on-chip capacitance and low
resonance frequency. Switching at high frequency with relatively low current,
SERDES will not affect common Power significantly (like in simulation results
in
http://www.designcon.com/2010/DCPDFs/10-TH2_Iliya_Zamek.pdf on Fig.9c, from 20
to 28ns); SERDES will cause just insignificant reduction of average Power
level,
or oscillations with very small amplitude (at low common PDN resonance
frequency).
Otherwise, Core will bring to the SERDES huge voltage variations (at low common
PDN resonance frequency) when Core logic’ switching event is following by idle
cycle (see Fig.9c, from 28 to 46ns, or Fig.9d). These big Power voltage
variations might cause the SERDES fail.
Other words, separate power makes Core and SERDES Power & timing variations
relatively independent, while they might be big.
Common power reduces significantly SERDES Power variations, but brings huge
Core
Power variations to the SERDES and it might fail to operate (more work has to
be
done regarding SERDES fail mode analysis).
Thanks Siming for starting this discussion.
Iliya
----- Original Message ----
From: Istvan Novak <istvan.novak@xxxxxxx>
To: Siming Pan <pansiming86@xxxxxxxxx>
Cc: Chris Cheng <Chris.Cheng@xxxxxxxx>; "si-list@xxxxxxxxxxxxx"
<si-list@xxxxxxxxxxxxx>
Sent: Mon, November 1, 2010 6:36:20 PM
Subject: [SI-LIST] Re: design of on-chip PDN
Hi Siming,
You also need to look at the maxim current draw, expected current
fluctuations and allowed
voltage noise on the core and IO rails. Maximum current draw is usually
higher in cores,
similarly on cores you can expect more current fluctuation; differential
IO rails tend to be
fairly quit both in terms of self-generated noise as well as in terms of
requirements of how
much noise coming from outside they may tolerate. Combining the two
rails may create more
noise than what the IO rail may tolerate, and your overall PDN design
might be simpler
and cheaper if you keep them separate all the way through. It all
depends on the numbers...
Regards,
Istvan Novak
Oracle
On 11/1/2010 9:22 PM, Siming Pan wrote:
> Hi All,
> Thanks very much for your reply.
> For the ASIC I am currently deal with, the voltage level for digital
> serdes and core are the same. So the reduction of common impedance seems to
> be the main reason that power nets for serdes and core are not connected.
> However, since the on-chip decaps for core is 100 times larger than it for
> digital serdes, common power net will significantly reduce SSN. How much
> impact for common impedance will the connection of power net cause?
>
> Regards,
> Siming
>
>
> 2010/11/1 Chris Cheng<Chris.Cheng@xxxxxxxx>
>
>> I've never dealt with an ASIC chip that doesn't have at least dual oxide to
>> separate core and I/O power distribution. Unless you are in the low power
>> business, there are many reasons why you want your I/O power higher than
>> your core voltage with all the new small geometry processes.
>> While common mode noise can be a concern, people have done tricks like on
>> die regulators and play with PLL loop bandwidth to mitigate these problems.
>>
>> Chris Cheng
>> Distinguished Technologist
>> 3PAR- an HP Company
>> HP StorageWorks Division
>>
>> www.hp.com
>> www.3PAR.com
>>
>> PS Go Giants !!!!!!!
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Siming Pan
>> Sent: Monday, November 01, 2010 4:10 PM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] design of on-chip PDN
>>
>> Hi All,
>> I have a basic question related to on-chip PDN design. Usually the supply
>> voltages are designed to be isolated for core, SERDES
>>
>> digital, analog, termination, etc. This design may isolate the SSN
>> couplings among each net. However, usually large on-chip decoupling
>>
>> capacitances are used for VDD core circuit. In the board design, we
>> connect
>> the power nets of VDD_core together with VDD_digital¡£
>>
>> Thus, switching noises generated from SERDES digital are suppressed by
>> large
>> on-chip decaps designed for core circuit. However,
>>
>> package inductances still play a bad role here to block the conducted path
>> between noise source formed by digital circuit and core
>>
>> capacitances. Then why not use one common power net as the supply power for
>> all the IC circuits, so that large on-chip decaps can be
>>
>> shared, if the voltage levels are the same?
>>
>> Regards,
>>
>> Siming Pan
>>
>>
>> --
>> Siming Pan
>>
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