[SI-LIST] Re: design of on-chip PDN

  • From: Istvan Novak <istvan.novak@xxxxxxx>
  • To: Siming Pan <pansiming86@xxxxxxxxx>
  • Date: Mon, 01 Nov 2010 21:36:20 -0400

Hi Siming,

You also need to look at the maxim current draw, expected current 
fluctuations and allowed
voltage noise on the core and IO rails. Maximum current draw is usually 
higher in cores,
similarly on cores you can expect more current fluctuation; differential 
IO rails tend to be
fairly quit both in terms of self-generated noise as well as in terms of 
requirements of how
much noise coming from outside they may tolerate.  Combining the two 
rails may create more
noise than what the IO rail may tolerate, and your overall PDN design 
might be simpler
and cheaper if you keep them separate all the way through.  It all 
depends on the numbers...

Regards,

Istvan Novak
Oracle


On 11/1/2010 9:22 PM, Siming Pan wrote:
> Hi All,
>      Thanks very much for your reply.
>      For the ASIC I am currently deal with, the voltage level for digital
> serdes and core are the same. So the reduction of common impedance seems to
> be the main reason that power nets for serdes and core are not connected.
> However, since the on-chip decaps for core is 100 times larger than it for
> digital serdes, common power net will significantly reduce SSN. How much
> impact for common impedance will the connection of power net cause?
>
> Regards,
> Siming
>
>
> 2010/11/1 Chris Cheng<Chris.Cheng@xxxxxxxx>
>
>> I've never dealt with an ASIC chip that doesn't have at least dual oxide to
>> separate core and I/O power distribution. Unless you are in the low power
>> business, there are many reasons why you want your I/O power higher than
>> your core voltage with all the new small geometry processes.
>> While common mode noise can be a concern, people have done tricks like on
>> die regulators and play with PLL loop bandwidth to mitigate these problems.
>>
>> Chris Cheng
>> Distinguished Technologist
>> 3PAR- an HP Company
>> HP StorageWorks Division
>>
>> www.hp.com
>> www.3PAR.com
>>
>> PS Go Giants !!!!!!!
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Siming Pan
>> Sent: Monday, November 01, 2010 4:10 PM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] design of on-chip PDN
>>
>> Hi All,
>>    I have a basic question related to on-chip PDN design. Usually the supply
>> voltages are designed to be isolated for core, SERDES
>>
>>   digital, analog, termination, etc. This design may isolate the SSN
>> couplings among each net. However, usually large on-chip decoupling
>>
>>   capacitances are used for VDD core circuit. In the board design, we
>> connect
>> the power nets of VDD_core together with VDD_digital¡£
>>
>> Thus, switching noises generated from SERDES digital are suppressed by
>> large
>> on-chip decaps designed for core circuit. However,
>>
>> package inductances  still play a bad role here to block the conducted path
>> between noise source formed by digital circuit and core
>>
>> capacitances. Then why not use one common power net as the supply power for
>> all the IC circuits, so that large on-chip decaps can be
>>
>> shared, if the voltage levels are the same?
>>
>> Regards,
>>
>> Siming Pan
>>
>>
>> --
>> Siming Pan
>>

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