[SI-LIST] design of on-chip PDN
- From: Siming Pan <pansiming86@xxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 1 Nov 2010 16:10:15 -0700
Hi All,
I have a basic question related to on-chip PDN design. Usually the supply
voltages are designed to be isolated for core, SERDES
digital, analog, termination, etc. This design may isolate the SSN
couplings among each net. However, usually large on-chip decoupling
capacitances are used for VDD core circuit. In the board design, we connect
the power nets of VDD_core together with VDD_digital¡£
Thus, switching noises generated from SERDES digital are suppressed by large
on-chip decaps designed for core circuit. However,
package inductances still play a bad role here to block the conducted path
between noise source formed by digital circuit and core
capacitances. Then why not use one common power net as the supply power for
all the IC circuits, so that large on-chip decaps can be
shared, if the voltage levels are the same?
Regards,
Siming Pan
--
Siming Pan
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