[SI-LIST] Re: design of on-chip PDN

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: Siming Pan <pansiming86@xxxxxxxxx>
  • Date: Mon, 01 Nov 2010 16:23:48 -0700

Common impedance.

Siming Pan wrote:
> Hi All,
>    I have a basic question related to on-chip PDN design. Usually the supply
> voltages are designed to be isolated for core, SERDES
>  digital, analog, termination, etc. This design may isolate the SSN
> couplings among each net. However, usually large on-chip decoupling
>  capacitances are used for VDD core circuit. In the board design, we connect
> the power nets of VDD_core together with VDD_digital¡£
> Thus, switching noises generated from SERDES digital are suppressed by large
> on-chip decaps designed for core circuit. However,
> package inductances  still play a bad role here to block the conducted path
> between noise source formed by digital circuit and core
> capacitances. Then why not use one common power net as the supply power for
> all the IC circuits, so that large on-chip decaps can be
> shared, if the voltage levels are the same?
> Regards,
> Siming Pan

Steve Weir
150 N. Center St. #211
Reno, NV  89501 

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