[SI-LIST] Re: SMPS capacitor
- From: Krunal Desai <movax@xxxxxxxxx>
- To: istvan.novak@xxxxxxxxxxx
- Date: Thu, 6 Mar 2014 23:24:29 -0800
On Thu, Feb 20, 2014 at 6:05 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx> wrote:
> Regarding evaluation and demo boards from vendors: we need to understand
> the purpose and limitations of those boards. The purpose is to
> demonstrate the correct operation of the circuit. The motivation is to
> show the ultimate benefits of the vendor parts, sometimes regardless of
> user constraints. This leads us to the limitations of the evaluation
> boards: there is no way for the vendor to create demo boards for the
> very large number of possible permutations resulting from different user
> applications and layout. The clamshell layout is actually one of the
> best possible arrangements for the converter itself: it minimizes loop
> inductance, can help to reduce parasitic ringings, maximize density and
> efficiency. We can use a clamshell layout when it does not upset
> anything on our board (nothing sensitive going through the same plane
> cavities) or when we can place the clamshell converter circuit into an
> isolated area of the board (isolation means that we cut the planes
> around the converter so that they dont carry the noise around).
Agreed Istvan; this demo board in question actually has long stubs off
the gate signals to facilitate probing, obviously not ideal for a real
application :)
> Regarding the placement of bulk capacitors: in fact there are
> conflicting requirements. The bulk capacitors handling the DC-DC
> converter output ripple current would need to be closer to the
> converter, whereas the bulk capacitors handling the load transients may
> need to be closer to the load. On a small plane shape this usually does
> not matter; it becomes a relevant question and dilemma at high current
> larger planes. Suggested solution: split the bulk capacitors and
> distribute them according to the occurrence of transients.
I have run into this issue now, with a very constrained layout where I
think I may be forced to place an output capacitor on the opposite
side of the board from the converter. The MOSFETs, inductor and gate
driver are all on the top layer, in addition to a 22uF + 0.1uF ceramic
output capacitor. If I place a healthy amount of vias (which I will
anyway to facilitate delivering power into the plane), what is the
mechanism of the cavity mode injection I may see if I have the 100uF
bulk output cap on the opposite side? Must I keep a healthy anti-pad
area on every layer to attempt to avoid noise injection?
The input to this converter is a solar array, which space constraints
may also force me to place the capacitors on the opposite side of the
board from the high-speed current loop.
Thanks,
Krunal
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