[SI-LIST] Re: SMPS capacitor
- From: DAVID CUTHBERT <telegrapher9@xxxxxxxxx>
- To: bowden.ivor@xxxxxxxxx
- Date: Mon, 17 Feb 2014 07:11:35 -0700
Ivor,
a SPICE model of the SMPS, filter, the path to the load, and the load
decoupling can provide insight into this. Two important parameters to
include are the decoupling cap inductance and the trace or plane inductance
between the SMPS and the load. The SMPS model need not be complete; it can
consist of the basic topology running open loop.
Load transients (load dump for example) can be explored by changing the
load current. The load can be simulated by a current source that abruptly
drops to zero or by a resistor with a series switch (a voltage controlled
switch or a FET).
Many SMPS output filters are simple L-C filters. For example, a buck
regulator inductor connected to the filter capacitor. This is the case if
the SMPS is right at the load. But when there is distance between the SMPS
and the load another L-C filter surfaces, the trace or plane inductance and
the decoupling capacitance at the load. This seems to be what you're asking
about.
If you need directions to calculate the trace or plane inductance I will
post them.
Dave Cuthbert
Rubidium Technology LLC (a consulting company)
EMC design, PS, instrumentation, and anything analog
On Mon, Feb 17, 2014 at 2:03 AM, Ivor Bowden <bowden.ivor@xxxxxxxxx> wrote:
> Hi SI Experts,
> I am interested in comments about SMPS capacitor placement /
> routing.
>
> I understand that given an SMPS and a Load, the ideal
> situation is to have SMPS bulk output capacitor close to
> SPMS / inductor sized to handle inductor ripple current;
> Load bulk input capacitor at load sized to hand load
> transient current; SMPS bulk input capacitor at SMPS input
> sized to handle peak inductor input current, considering
> SMPS input supply impedance. Undersized SMPS input capacitor
> can result in switching noise on SMPS input supply power /
> ground planes. SMPS sense feedback can connect to load to
> compensate for power path IR drop if delay doesn't
> destabilize loop control.
>
> Comments on preceding welcome.
>
> Example could be 4 V 1 MHz SMPS supply 1 V and 1 A to CPU /
> FPGA device, with 1/3 A inductor ripple current, using large
> value (10-100 uF) MLCC.
>
> Consider case where due to design constraints SMPS bulk
> output capacitor and Load bulk input capacitor required to
> be same physical device. Say SMPS and Load are relatively
> close together, a few cm. Say Load has appropriate local
> decaps for HF transients. If capacitor is closer to SMPS
> inductor then inductor ripple current loop is smaller; if
> capacitor is closer to load then load transient current loop
> is smaller. If selected to place capacitor close to load to
> better supply load transients, what are practical effects to
> expect from longer SMPS inductor ripple current loop in
> terms of overall PDN integrity, EMI, and switching crosstalk
> noise to adjacent signals?
>
> I understand specific answers depend on specific circuits, I
> seek general comments about potential issues and
> resolutions, such as how common is it to place SMPS output
> bulk capacitors only at load and what effects to expect for
> those cases?
>
> Or to phrase another way, (how) would you make case for
> separate output and load bulk caps?
>
> Thank you,
>
> Ivor Bowden
>
>
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