[SI-LIST] Re: SMPS capacitor
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Ravinder.Ajmani@xxxxxxxx
- Date: Wed, 19 Feb 2014 18:11:53 -0500
Ravi,
Lower current integrated SMPS chips will have even faster Trise and Tfall
times. Efficiency calculations for the LM26420 ( a dual output 2A
integrated SMPS) use a typical value of 1.5 ns.
http://www.ti.com/lit/ds/symlink/lm26420-q1.pdf
regards,
Scott
On Wed, Feb 19, 2014 at 5:49 PM, <Ravinder.Ajmani@xxxxxxxx> wrote:
>
> Hi Scott,
>
> Larry's example was for a processor drawing 1A current. I doubt if such a
> processor will require the type of power supply you have described.
>
> Regards
> Ravinder Ajmani
>
> HGST, a Western Digital company
> 5601 Great Oaks Pkwy
> San Jose, CA 95119-1003
> ravinder.ajmani@xxxxxxxx
>
>
>
> *Scott McMorrow <scott@xxxxxxxxxxxxx <scott@xxxxxxxxxxxxx>>*
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
> 02/19/2014 02:24 PM
> Please respond to
> scott@xxxxxxxxxxxxx
>
> To
> Ravinder.Ajmani@xxxxxxxx
> cc
> larrys@xxxxxxxxxxxxxxxx, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
> Subject
> [SI-LIST] Re: SMPS capacitor
>
>
>
>
> Fast rise time leads to high efficiency. The power n-mosfets for 3-phase
> processor power supplies I'm familiar with have a switch rise/fall time of
> 6 to 8 ns. They tend to ring like a bell in the 100 to 160 MHz region and
> radiate if not correctly bypassed at the input.
>
> On Wed, Feb 19, 2014 at 5:00 PM, <Ravinder.Ajmani@xxxxxxxx> wrote:
>
> > Hi Larry,
> > I am unable to understand how can the FETs switch in 1 nSec, when the
> > common SMPS switches at 1 - 2 MHz.
> >
> > I will appreciate if you can clarify this.
> >
> > Thanks.
> >
> > Regards
> > Ravinder Ajmani
> >
> > HGST, a Western Digital company
> > 5601 Great Oaks Pkwy
> > San Jose, CA 95119-1003
> > ravinder.ajmani@xxxxxxxx
> >
> >
> >
> >
> > "Smith, Larry" <larrys@xxxxxxxxxxxxxxxx>
> > Sent by: si-list-bounce@xxxxxxxxxxxxx
> > 02/19/2014 09:36 AM
> > Please respond to
> > larrys@xxxxxxxxxxxxxxxx
> >
> >
> > To
> > "bowden.ivor@xxxxxxxxx" <bowden.ivor@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx"
> > <si-list@xxxxxxxxxxxxx>
> > cc
> >
> > Subject
> > [SI-LIST] Re: SMPS capacitor
> >
> >
> >
> >
> >
> >
> > Ivor - some hand calculations can give good insight into the problem.
> > Several posters on this thread have mentioned the di/dt but it is not
> > really that much of a problem for the L C output loop. Using the
> > parameters below and assuming a 1 uH inductor, di/dt = V/L = (4V-1V)/1uH
> > 3 A/uSec. This is not trivial but it is not as big as a single DDR net
>
> > from a few years ago that might have a di/dt of 15mA/1nSec = 15A/uSec, 5x
> > bigger. We send multiple DDR nets through PCB cavities all the time.
> >
> > The switched node upstream of the working inductor has a big dV/dt,
> > possibly 4V/nSec. The trace between FET switches and inductor should be
> > short for that reason. Both dV/dt and dI/dt downstream of the working
> > inductor are fairly tame. The FET switches should make and break quickly
> > and efficiently and allow continuous current to flow around the output
> > loop with tightly coupled currents and return currents. The power plane
> > (trace) inductance and mounted load cap inductance is probably less than
> > 10nH or 1% of the working inductance. There will be some switching noise
> > downstream of the working inductor but it is not excessive. Most of the
> > voltage drop is across the working inductor.
> >
> > As several posters have already mentioned, the problem is with the SMPS
> > input capacitor. If the FETs switch in 1nSec and the CPU load is 1A, the
> > di/dt in the input capacitor loop is 1A/nSec = 1000A/uSec which is 333x
> > bigger than in the output loop. Be real careful with the mounting of
> that
> > one!
> >
> > Regards,
> > Larry Smith
> >
> > PS - I hope you enjoy the Altera PDN tool. Ravi, Coung and I put that
> > together several years ago.
> >
> > -------------- original post -----------------
> > Hi SI Experts,
> > I am interested in comments about SMPS capacitor placement / routing.
> >
> > I understand that given an SMPS and a Load, the ideal situation is to
> have
> > SMPS bulk output capacitor close to SPMS / inductor sized to handle
> > inductor ripple current; Load bulk input capacitor at load sized to hand
> > load transient current; SMPS bulk input capacitor at SMPS input sized to
> > handle peak inductor input current, considering SMPS input supply
> > impedance. Undersized SMPS input capacitor can result in switching noise
> > on SMPS input supply power / ground planes. SMPS sense feedback can
> > connect to load to compensate for power path IR drop if delay doesn't
> > destabilize loop control.
> >
> > Comments on preceding welcome.
> >
> > Example could be 4 V 1 MHz SMPS supply 1 V and 1 A to CPU / FPGA device,
> > with 1/3 A inductor ripple current, using large value (10-100 uF) MLCC.
> >
> > Consider case where due to design constraints SMPS bulk output capacitor
> > and Load bulk input capacitor required to be same physical device. Say
> > SMPS and Load are relatively close together, a few cm. Say Load has
> > appropriate local decaps for HF transients. If capacitor is closer to
> SMPS
> > inductor then inductor ripple current loop is smaller; if capacitor is
> > closer to load then load transient current loop is smaller. If selected
> to
> > place capacitor close to load to better supply load transients, what are
> > practical effects to expect from longer SMPS inductor ripple current loop
> > in terms of overall PDN integrity, EMI, and switching crosstalk noise to
> > adjacent signals?
> >
> > I understand specific answers depend on specific circuits, I seek general
> > comments about potential issues and resolutions, such as how common is it
> > to place SMPS output bulk capacitors only at load and what effects to
> > expect for those cases?
> >
> > Or to phrase another way, (how) would you make case for separate output
> > and load bulk caps?
> >
> > Thank you,
> >
> > Ivor Bowden
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Ivor Bowden
> > Sent: Wednesday, February 19, 2014 6:14 AM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: SMPS capacitor
> >
> > Thanks all responders for the insights and information. I mostly heard
> > what I expected, and it is good to have consensus. I think Steve summed
> it
> > up well, quote below.
> > Side note, Google "Altera PDN" found "device agnostic" PDN worksheet tool
> > on the Altera website available for free download along with user guide
> > and application note pdf files. Any other suggestions for "free" tools to
> > help estimate planes, trace and via inductance / impedance welcome.
> >
> > Regards, Ivor
> >
> > On 2/17/2014 4:44 PM, steve weir wrote:
> > > Proper engineering practice never requires justification. Deviation
> > > from proper practice requires rigorous justification.
> >
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>
> --
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 16 Stormy Brook Rd
> Falmouth, ME 04105
>
> (401) 284-1827 Business
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> http://www.teraspeed.com
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> Teraspeed® is the registered service mark of
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--
Scott McMorrow
Teraspeed Consulting Group LLC
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
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