Hi All, Now I do some board timing simulations . I got the hspice = model and ibis model for same buffer. Then I set a test fixture(Ex. Cref=3D15pf,Rref=3D1E6,Vref=3D3.3V),I contrast the simulation result of = buffer dealy using hspice model and ibis model. I found there is a little big diffrence between them. So when translate hspice model to ibis model,how to consider about the buffer deley issue? =20 Should I trust the buffer delay value from ibis model = simulation? Best Regards. Yan Hang Huawei Technology 086-21=A3=AD68644808=A3=AD24043 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu