[SI-LIST] Re: Buffer delay

  • From: "YAK LHASA" <lhasayak@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 21 Nov 2006 22:20:58 +0800

read Michael Mirmak's reply word by word. then think about the timing u
refer to.
On 17/11/06, raj singh <forsilist@xxxxxxxxx> wrote:
>
> Hspice delays should be accurate and in general more than ibis. Better to
> use ibis only for SI sims and not for timing.
>
>   regards
>   Raj
> yan hang <yang@xxxxxxxxxx> wrote:
>
> Hi All,
> Now I do some board timing simulations . I got the hspice =
> model
> and ibis model for same buffer. Then I set a test fixture(Ex.
> Cref=3D15pf,Rref=3D1E6,Vref=3D3.3V),I contrast the simulation result of =
> buffer
> dealy using hspice model and ibis model. I found there is a little big
> diffrence between them.
> So when translate hspice model to ibis model,how to consider
> about the buffer deley issue? =20
> Should I trust the buffer delay value from ibis model =
> simulation?
>
> Best Regards.
>
> Yan Hang
> Huawei Technology
> 086-21=A3=AD68644808=A3=AD24043
>
>
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