[SI-LIST] Re: Buffer delay
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 21 Nov 2006 10:21:45 -0800
Hello everyone,
There have been lots of good points made on this topic, but
one was not mentioned yet which I believe is a pretty important
one to remember.
It is certainly possible to include the internal delays of a
buffer in the IBIS model's V-t curves but one needs to consider
the way IBIS simulators work. For example, if a V-t curve
consists of say 2 ns delay before the actual edge begins to
move, and the duration of that edge is say only 100 ps long,
and this device is running at such high frequencies that the
clock period is say 500 ps, then you may not get any output at
the pad of this device in your simulation. Why? Simply because
the clock is changing before the simulator ever reaches the end
of the "active part" of the V-t curve. In plain language I
usually call this over clocking. For this reason, the rule of
thumb recommendation I usually make is to have the shortest=20
possible V-t curves, and deal with the buffer delays elsewhere.
Arpad
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of David Lieby
Sent: Tuesday, November 21, 2006 7:49 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay
Having accurate timing in an IBIS file, say from the input to a buffer
to the die pad for that buffer on the silicon is interesting. It is
also fraught with pitfalls. If you are interested in _all_ the delays
in the system, you need to draw the line somewhere. While not going
into where to place the responsibility for complete timing analysis of a
circuit, there are some things in IBIS that you need to be careful with.
If your IBIS file contains timing information for the entire time from
input to the buffer to the end of the transition and ringing at the end
of the transient event you wind up with a whole lot of time points that
are meaningless. I have seen some ECL driver models where, because of
the decimation of the actual transition data to fit into a reasonable
size table, the actual event had only about 5 points. That amount of
data for the simulator is sadly insufficient. If you look at a plot of
the data there is nearly nothing to look at. =3D20
Also, if you are doing a Spice Simulation, with an IBIS model like that,
there is a lot of time going to waste in the simulation because each
time step is analyzed while nothing is happening. This sort of thing
could lead to a good relaxed day while you are waiting for the
simulation to run. On the other hand it is fun to get the job done and
have some time at home with the family.
dav0
David Lieby
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of zheng qi
Sent: Monday, November 20, 2006 5:17 PM
To: michael.mirmak@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay
I would agree with Mirmak michael about accuracy of IBIS vs Spice and
on 2006 shanghai ibis summit i had shown some evaluation result ,
But..but as to timing issues i have the same question as yan hang
mentioned and i also brought it on 2005 shenzhen ibis summit .
there i adviced that when doing more tight timing analysis maybe
core to core timing is more suitable.
The problem here is when comparing with IBIS and Hspice model output
that the t waveform under test load condition does exist a timing
offset,and sometimes up to 1ns. So if the model had well-constructed
as Michael Mirmak said , everything will be OK , But the fact is
that these type of 'good ' model seems does not exist , is it true ??
If it is, In what extent does we can believe with the timing
analysis
of IBIS ?
Best regards
zheng qi
qzheng@xxxxxxxxxxxxxxxx
Best Regards
qzheng
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