[SI-LIST] Re: Buffer delay

  • From: "zheng qi" <qzheng.hb@xxxxxxxxx>
  • To: michael.mirmak@xxxxxxxxx
  • Date: Tue, 21 Nov 2006 09:17:11 +0800

I would agree with Mirmak michael about accuracy of IBIS vs Spice and
on  2006 shanghai ibis summit i had  shown some evaluation result ,
But..but as  to timing issues i have the same  question as yan hang
mentioned and i also  brought  it on 2005 shenzhen  ibis summit .
there i adviced that when doing  more tight  timing analysis maybe
core to core  timing is more suitable.

The problem here is when comparing with IBIS and Hspice model output
that  the t waveform under test load condition does exist a timing
offset,and  sometimes up to 1ns.  So if the model had well-constructed
 as Michael Mirmak said ,  everything will be OK , But the fact is
that these type of 'good ' model seems does not exist , is it true ??
 If  it is,  In what extent does we can believe with the timing
analysis
of IBIS ?

Best regards
zheng qi
qzheng@xxxxxxxxxxxxxxxx




Best Regards
qzheng
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