[SI-LIST] Re: Buffer delay
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: "Mirmak, Michael" <michael.mirmak@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 21 Nov 2006 12:30:06 -0800
I'd like to add a couple comments to what Michael said. I'm sure most of
us already
understand the concept of flight time, but it doesn't hurt to mention it
once in a
while, when such topics come up. =20
In the timing methodologies I'm familiar with the IBIS simulations are
designed
to capture flight time from the buffer output to receiver input.
This flight time is obtained by subtracting the buffer delay into the
test load,
obtained from an IBIS simulation, from the overall delay seen in an IBIS
simulation
into the actual load topology, with both simulations launched in
parallel at t0.
The process of subtracting out IBIS buffer delay then normalizes the
flight time for
the random delay in the IBIS model V-T curves and leaves you with flight
time.=20
The flight time then includes the prop delay from driver output to
reciever, plus the
delta in driver tCO between that defined in the driver characterization
sims, generally
done at transistor level, and that which is seen when driving into the
actual load.
You can then take this flight time and add it to the characterized tCO
of the driver
to calculate the overall delay from driver input to receiver. However,
since
most devices provide AC timing specs defined at the pad or pin, which
already comprehend
the tCO of the driver, this summation is generally not neccessary. Most
timing analysis
I am involved in uses only AC specs and flight times or skews to
calcualte timing margins.
In addition, IBIS models must be constructed with V-T curves that fully
switch
within the minimum switching period seen in simulation. For square wave
stimulus this would
be one-half the switching period. Otherwise you risk inconsistent
results, due to the switching
into an unfinished edge phenomenon. Something that is not handled
consistently in all
simulators. Therefore, trying to add a true tCO delay to the leading
edge of the V-T curves
just makes it that much more difficult to capture the transistion within
the switching
interval. On many interfaces, such as DDR2, its a challenge to capture
these edges
without distortion, due to the limited slew rate of teh drivers.=20
Whether this problem is addressed better in teh multi-lingual IBIS
extensiosn is not
something I have inquired about, but in traditional V-T curve based IBIS
it is an importany
consideration.=20
Brian P. Moran
Intel Corporation=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Mirmak, Michael
Sent: Friday, November 17, 2006 10:54 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay
All,
I would disagree somewhat with the conclusions regarding accuracy and
IBIS vs. SPICE models.
We must be very careful in how the words "buffer delay" are being used
here. For system analyses, many tools define "buffer delay" as the time
elapsed between the start of *simulation* and the crossing of a defined
measurement voltage, using a defined measurement load. For a
well-constructed IBIS model, even using traditional V-t and I-V tables,
excellent correlation to SPICE transistor-level models may be obtained
for buffer delay in this sense. As a result, IBIS could be -- and is --
used for system timing analysis where the timing equations use buffer
delay.
Timings for driver outputs relative to an incoming clock signal -- for
example, "Tvalid" or "Tco" (Time clock to out) -- could not be directly
simulated under traditional IBIS, as the format does not include the
data path from the incoming clock node to the driver, to "latch" the
signal out. =3D20
Advanced IBIS models, such as those under IBIS 4.1 and 4.2 using
multi-lingual extensions, may contain these driver clock-to-out
connections and paths, should the model author choose to include them.
A direct comparison of clock-to-out waveforms between this kind of
advanced IBIS model and a SPICE transistor model may then be obtained.
I hope this helps!
- Michael Mirmak
Intel Corp.
Chair, EIA IBIS Open Forum
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of raj singh
Sent: Friday, November 17, 2006 01:34
To: yang@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: liuweidong@xxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay
Hspice delays should be accurate and in general more than ibis. Better
to use ibis only for SI sims and not for timing.
=3D20
regards
Raj
yan hang <yang@xxxxxxxxxx> wrote:
=3D20
Hi All,
Now I do some board timing simulations . I got the hspice model and ibis
model for same buffer. Then I set a test fixture(Ex.
Cref=3D3D15pf,Rref=3D3D1E6,Vref=3D3D3.3V),I contrast the simulation =
result of
=3D buffer delay using hspice model and ibis model. I found there is a
little big diffrence between them.
So when translate hspice model to ibis model,how to consider about the
buffer deley issue?=3D20
Should I trust the buffer delay value from ibis model simulation?
Best Regards.
Yan Hang
Huawei Technology
086-21=3D3DA3=3D3DAD68644808=3D3DA3=3D3DAD24043
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=20
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