[SI-LIST] Re: Buffer delay

  • From: "Lynne D. Green" <lgreen22@xxxxxxxxxxxxxx>
  • To: <forsilist@xxxxxxxxx>, <yang@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 17 Nov 2006 11:35:42 -0800

Hello, Yan Hang,

IBIS and SPICE do not have the same Time=0 reference, due to the way SI
tools trigger I/O inputs.  This means that there is a time offset between
the two waveforms.

This offset can be corrected for by simulating the load [Vmeas, Rref, Cref].
This delay offset can then be used to adjust the delay in other simulations.
Many SI tools have automated this process.

A good paper on this is http://pcdandm.com/cms/content/view/2800/95/.  There
is also a HyperLynx Application Note, referenced in that paper.

Best regards,

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of raj singh
Sent: Friday, November 17, 2006 1:34 AM
To: yang@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: liuweidong@xxxxxxxxxx
Subject: [SI-LIST] Re: Buffer delay

Hspice delays should be accurate and in general more than ibis. Better to
use ibis only for SI sims and not for timing.
yan hang <yang@xxxxxxxxxx> wrote:
Hi All,
Now I do some board timing simulations . I got the hspice = model and ibis
model for same buffer. Then I set a test fixture(Ex.
Cref=3D15pf,Rref=3D1E6,Vref=3D3.3V),I contrast the simulation result of =
buffer dealy using hspice model and ibis model. I found there is a little
big diffrence between them.
So when translate hspice model to ibis model,how to consider about the
buffer deley issue? =20 Should I trust the buffer delay value from ibis
model = simulation?

Best Regards.

Yan Hang
Huawei Technology

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