[PCB_FORUM] Re: how do YOU handle component spacing rules?
- From: "Ritter, Alan" <Alan.Ritter@xxxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Tue, 8 Jun 2004 13:56:28 -0400
<flame>
George, you hit the nail on the head about the disconnect between Cadence
and real-world designers. Now, I'm an EE by trade, but I also do board
layout and (in today's "do more with less" world) documentation. (We won't
speculate as to the advisability of having your senior engineering staff
spending their time fixing drawings...)
I've always said that nobody in Cadence R&D has EVER had to put copper on
fiberglass...they think that a file out the back end of their software is
the end of the process. Look at all of the issues with negative planes, the
inability to PROPERLY join multiple planes (AGND/DGND just for one example)
and a whole host of other issues critical to making a board actually WORK as
the engineer intended.
I know that a bunch of the Cadence aps engineers ARE designers, and they
whine about the same stuff (would you like some cheese to go with that
whine, sir?) to no avail. All we can do is keep pounding on R&D and hope
they listen...having them halfway around the world from the customers
certainly won't help a bit!
</flame>
/s/jar (alan.ritter@xxxxxxxxxx)
http://www.mtritter.org
Bausch & Lomb
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