All: I am not sure if I saw it stated clearly anywhere along this topic-thread... But Allegro does provide component-type to component-type clearance checking under DFA checks (component clearance audit) albeit a separate batch check until on-line comp-comp is enabled at SPB 15.5. Certainly this check can be launched anytime before end of design cycle. Anyone familiar with Mentor tools will definitely find this "lack of robustness" for comp to comp matrix checking as a "pain in the placement process" compared to the ease of on-line placement checking, especially for high "pad/area" designs where excess component clearance is scarce. At this moment a Cadence AE is putting together a mechanism to facilitate the capture of the clearance rules matrix, say from an excel spreadsheet matrix, that can be easily loaded into the DFA checking values format. This mechanism will have to suffice until 15.5. If this level of component clearance applies to you, just as an FYI, you may also want to ensure that you have a library maintained property dedicated to this task. ie. Component_type = BGA, 0402,1206, SMD_under_2mm, etc. These properties can be applicable to the footprint. Michael Baumstark Staff PCB Designer - Rapid Product Realization Center Plantation, FL USA 33322-9947 Desk: 1954-723-8276 Intra: http://rprc.mot.com web: http://www.motorola.com --------------^------------------^-----------------^------------------^-------------- >---^-.--- >---^-.--- >---^-.--- Motorola Internal Use [ ] Motorola Confidential Proprietary [ ] -----Original Message----- From: Gene Carman [mailto:gcarman@xxxxxxxxxxxxxxx] Sent: Tuesday, June 08, 2004 1:27 PM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules? These tools are such that they only run post design. I need tools that will run in the design upfront that can aid with placement based on different manufactures' placement rules. I cannot afford the time hit of preparing a total design to Gerber before I discover component placement problems. I would rather prevent problems early in the design than discover same later. An ounce of prevention... Quite frankly I am surprised that placement rules by component type are not already part of the Allegro tools. Having used other tools in the past, it is really interesting on the issues that various EDA companies focus on. I don't know how many times some AE has tried to tell me about cross talk test/simulators and 3D RF solvers and "silicon to board solutions", while their tools would not let me do something as simple as making an arc by a defined center and start and stop angles, or simply making a fabrication panel... common day to day requests in commercial design. (I believe we had an arc discussion last week with regard to the new fill features... not the same issue I bring up here, but... ) To paraphrase a former presidential candidate: "its the metal, stupid." Meaning: controlling all aspects of PWB copper is #1 priority. -----Original Message----- From: Chan [mailto:chan@xxxxxxxxxxxxxxx] Sent: Tuesday, June 08, 2004 10:13 AM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules? Adiva is providing a DFA check tools which can directly interface with Allegro. Please check with their website for more info. http://www.adiva.com Cheers, Chan -----Original Message----- From: Tim Woytek [mailto:Tim.Woytek@xxxxxxxxxx] Sent: Wednesday, June 09, 2004 12:49 AM To: 'icu-pcb-forum@xxxxxxxxxxxxx' Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules? I am looking forward to these new checks. Currently, we do placement checks in VALOR as well. It takes time to do these valor checks anyway,,,,so if I can accomplish the same thing in Allegro (and not need to tie up a VALOR license) then great. I assume they will have the DRC mode switch(s) to adjust accordingly. As for the multi-threading,,,,,,I would like to second that vote as well. Regards, Tim Woytek PCB Project Manager/Senior PCB Designer Plexus Corporation Technology Group http://www.plexus.com Office# 214-712-7316 Fax# 214-712-7301 Mobile# 254-624-3307 tim.woytek@xxxxxxxxxx -----Original Message----- From: george.h.patrick@xxxxxxxxxxxxxx [mailto:george.h.patrick@xxxxxxxxxxxxxx] Sent: Tuesday, June 08, 2004 11:42 AM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules? On-line placement checks would be nice, but I have a concern about adding another layer of on-line DRC checking. As it is, it takes 45 minutes to an hour to do a dbdoctor run on some of our boards, and this is on dual Xeon PCs with 1 GB of RAM. Creating and updating modules takes similar times. Another layer of DRC checking is going to slow the process down even more. It would help if Cadence would start using some multi-threading in Allegro so it would operate more efficiently in conjunction with adding additional DRC checks that will slow things down even more. Even those with single processors would benefit, at least those with hyper-threading processors. The other option, of course, is getting some smaller boards to work on :) -- George Patrick Tektronix, Inc. Central Engineering, PCB Design Group P.O. Box 500, M/S 39-512 Beaverton, OR 97077-0001 Phone: 503-627-5272 Fax: 503-627-5587 http://www.tektronix.com http://www.pcb-designer.com It's my opinion, not Tektronix' -----Original Message----- From: Gene Carman [mailto:gcarman@xxxxxxxxxxxxxxx] Sent: Tuesday, June 08, 2004 09:19 To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules? "Worst case" is different for different customers depending on their manufacturing equipment and their ultimate goal for their products. So what is worst case for one customer, could be a walk in the park for another... Sort of like line and space rules: some can do 3/3 mils and do not charge a premium, others can barely do 4/4. The 3/3 guys want small handheld products, thus they consider 3/3 a walk in the park. The 4/4 guys want cheap products, so they push for 4/5 for cheaper processes. Some can do stacked microvias, others cannot. It all comes down to design density and the customer goal. I will have to play with the DFA rules, but it sure would be nice to have these as true on line DRCs. (I know, I know... future release) Someone suggested building in the limits into my place bound layer... great idea... lessee that means modify the library for each design... oh yeah, that sounds expedient. Sorry, but that just does not sound like the best way to do things. Being able to change a variable in a DRC type set of rules is the right way. I notice that this is planned for the future. Thanks all. -----Original Message----- From: Kevin McCowan [mailto:kmccowan@xxxxxxxxxxxxxx] Sent: Tuesday, June 08, 2004 6:16 AM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules? Why not just make everything worst case? If you can do it that way it seems as though everyone would be happy. It might cause you some distress, but you wouldn't have to make different parts for different customers and the rules would apply. It has been they way I have always worked and it hurts a little, sure, but it solves the problem without a lot of tom-foolery. And while you are figuring that out, why not alert Cadence that this type of ruleset would be extremely useful to you. I would certainly welcome rules of this type added to the already formidable toolset we have. Good luck, Kevin McCowan SR. PCB Designer TSI Telsys > -----Original Message----- > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Gene Carman > Sent: Tuesday, June 08, 2004 12:00 AM > To: icu-pcb-forum@xxxxxxxxxxxxx > Subject: [PCB_FORUM] how do YOU handle component spacing rules? > > > Is there a way to set a component type to component type rule? What I = > mean is that certain component types tend to have different rules... = > such as 0402 to 0402 verses 0402 to SOT or BGA. > > The only rules I have found are pad to pad... which does not allow for = > different type rules. > > I spoke to some other designers and they offered two solutions: One is = > to build visual indicators into the parts so you can tell if your 0402 = > is too close to another 0402 or BGA... great, no DRC there. The other = > solution is simply use grids and place them... again no DRC. > > I have different customers that require different spacings. One = > customer wants 20 mils between 0402 pads, another wants 25. Customer 1 = > wants 50 mils between BGA and 0402, customer 2 wants 40 mils between BGA = > and any other comp. =20 > > With other tools I had the ability to assign components to a component = > type and then assign rules of type to type. I don't see a way to do = > that in Allegro (15.1) (very similar to net type rules in Allegro, for = > component to component spacing) > > What do you do? > ----------------------------------------------------------- > To subscribe/unsubscribe: > Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx > with a subject of subscribe or unsubscribe > > To view the archives of this list please login at > //www.freelists.org. Our list name is icu-pcb-forum > or go to //www.freelists.org/archives/icu-pcb-forum/ > > Problems or Questions: > Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx > > Want to post a job listing ? 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