These tools are such that they only run post design. I need tools that will run in the design upfront that can aid with placement based on different manufactures' placement rules. I cannot afford the time hit of preparing a total design to Gerber before I discover component placement problems.
I would rather prevent problems early in the design than discover same later.
An ounce of prevention...
Quite frankly I am surprised that placement rules by component type are not already part of the Allegro tools.
Having used other tools in the past, it is really interesting on the issues that various EDA companies focus on.
I don't know how many times some AE has tried to tell me about cross talk test/simulators and 3D RF solvers and "silicon to board solutions", while their tools would not let me do something as simple as making an arc by a defined center and start and stop angles, or simply making a fabrication panel... common day to day requests in commercial design. (I believe we had an arc discussion last week with regard to the new fill features... not the same issue I bring up here, but... )
To paraphrase a former presidential candidate: "its the metal, stupid."
Meaning: controlling all aspects of PWB copper is #1 priority.
-----Original Message-----
From: Chan [mailto:chan@xxxxxxxxxxxxxxx]
Sent: Tuesday, June 08, 2004 10:13 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules?
Adiva is providing a DFA check tools which can directly interface with
Allegro. Please check with their website for more info.
http://www.adiva.com
Cheers,
Chan
-----Original Message-----
From: Tim Woytek [mailto:Tim.Woytek@xxxxxxxxxx]
Sent: Wednesday, June 09, 2004 12:49 AM
To: 'icu-pcb-forum@xxxxxxxxxxxxx'
Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules?
I am looking forward to these new checks. Currently, we do placement
checks
in VALOR as well. It takes time to do these valor checks anyway,,,,so
if I
can accomplish the same thing in Allegro (and not need to tie up a VALOR
license) then great. I assume they will have the DRC mode switch(s) to
adjust accordingly.
As for the multi-threading,,,,,,I would like to second that vote as
well.
Regards,
Tim Woytek
PCB Project Manager/Senior PCB Designer
Plexus Corporation
Technology Group
http://www.plexus.com
Office# 214-712-7316 Fax# 214-712-7301
Mobile# 254-624-3307 tim.woytek@xxxxxxxxxx
-----Original Message-----
From: george.h.patrick@xxxxxxxxxxxxxx
[mailto:george.h.patrick@xxxxxxxxxxxxxx]
Sent: Tuesday, June 08, 2004 11:42 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: how do YOU handle component spacing rules?
On-line placement checks would be nice, but I have a concern about
adding
another layer of on-line DRC checking.
As it is, it takes 45 minutes to an hour to do a dbdoctor run on some of
our
boards, and this is on dual Xeon PCs with 1 GB of RAM. Creating and
updating modules takes similar times. Another layer of DRC checking is
going to slow the process down even more.
It would help if Cadence would start using some multi-threading in
Allegro
so it would operate more efficiently in conjunction with adding
additional
DRC checks that will slow things down even more. Even those with single
processors would benefit, at least those with hyper-threading
processors.
The other option, of course, is getting some smaller boards to work on
:)
