[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc

MC,

With all the recent postings I tried to show Chris that even if someone
follows good engineering practices (referencing the correct plane),
beyond a certain trace density and edge rate, it may make perfect sense
to use thin power-ground laminates.  Of course you dont use them
if you can avoid it by properly engineering the board.  And there is
a gray area where the tradeoffs wont point very clearly one way or
the other.

I agree with the first half of your statement, but not completely with
the second half of it.  If you change a G-S-PWR stackup portion to
G-PWR-S-G, you dont have to change the spacing between S and
PWR, so the trace inductance wrt PWR wont change (the total trace
loop inductance wont change anyway if you use the same dielectric
and same trace impedance).  The G-PWR inductance in the second
stackup portion is so much smaller than the trace inductance, that it
wont really change anything in that regard.

Regards,

Istvan


----- Original Message -----
From: "lenaw" <lenaw@xxxxxxxxx>
To: <istvan.novak@xxxxxxxxxxxxxxxx>; "Chris Cheng"
<Chris.Cheng@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, February 11, 2004 11:22 PM
Subject: Re: [SI-LIST] Re: Stack up for EMI reduction, plane resonance and
u-strip radiation etc etc


> Istvan:
>            On (b) my opinion is that if you want to reduce the
power/ground
> bounce, you have to reduce the total effective inductance of the
> power/ground planes ( assume you have no bond wire and use flip-chip
> technology to connect the die to the package ) and it depends on what kind
> of buffer technology you are using, signals on top of a pair of closely
> coupled power/ground reference may not be the best solution because you
need
> the strong mutual inductance between the signal and power or ground planes
> to reduce your total effective inductance during SSO. Just my 2cents.
>
>
> Regards,
> MC
>


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