[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc

  • From: "lenaw" <lenaw@xxxxxxxxx>
  • To: <weirsp@xxxxxxxxxx>, <istvan.novak@xxxxxxxxxxxxxxxx>,"Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 11 Feb 2004 22:41:00 -0600

Steve:
          Please try to locate one of those papers published in IEEE by Dr.
John Prince and his students from University of Arizona in Tuscon in the
early 90s related to calculation of effective inductance in SSO simulation.
In general the effective inductance of a power or ground pin is the sum of
the partial self inductance of itself minus the sum of all the partial
mutual inductance of the signal pins that share the common power or ground
pin. That is why PEEC is wonderful to handle SSO analysis in spice as long
as you connect the ideal ground node correctly. Correct me if it is not
right.

Regards,
MC

----- Original Message ----- 
From: "steve weir" <weirsp@xxxxxxxxxx>
To: <lenaw@xxxxxxxxx>; <istvan.novak@xxxxxxxxxxxxxxxx>; "Chris Cheng"
<Chris.Cheng@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, February 11, 2004 10:32 PM
Subject: [SI-LIST] Re: Stack up for EMI reduction, plane resonance and
u-strip radiation etc etc


> MC, how are you going to reduce inductance other than by reducing plane
> separation?
>
> Regards,
>
>
> Steve.
> At 10:22 PM 2/11/2004 -0600, lenaw wrote:
> >Istvan:
> >            On (b) my opinion is that if you want to reduce the
power/ground
> >bounce, you have to reduce the total effective inductance of the
> >power/ground planes ( assume you have no bond wire and use flip-chip
> >technology to connect the die to the package ) and it depends on what
kind
> >of buffer technology you are using, signals on top of a pair of closely
> >coupled power/ground reference may not be the best solution because you
need
> >the strong mutual inductance between the signal and power or ground
planes
> >to reduce your total effective inductance during SSO. Just my 2cents.
> >
> >
> >Regards,
> >MC
> >
> >----- Original Message -----
> >From: "Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>
> >To: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> >Sent: Wednesday, February 11, 2004 9:59 PM
> >Subject: [SI-LIST] Re: Stack up for EMI reduction, plane resonance and
> >u-strip radiation etc etc
> >
> >
> > > Chris,
> > >
> > > > a) If your plane reference is so limited and crowed with highspeed
> >traces
> > > > that it can not provide the effective capacitance, it will exhibit
> >itself
> > > as
> > > > both xtalk and power/gnd bounce problem. The image current starts to
> > > overlap
> > > > each other and either add or subtract from each other. This is an
> > > observable
> > > > problem in most signal traces in organic packages. But I will turn
the
> > > table
> > > > around and ask you, how could your fancy capacitor or thin core
plane
> >help
> > > > if they are electrically further from the reference planes ? It's
like
> > > > challenging my Covertte saying "hey, I bet you can't drive this car
at
> > > > 300mph" while you are sitting on a pintle.
> > >
> > > So I think we are in agreement here that if trace density is
increases,
> > > beyond
> > > a certain point we will have power/ground bounce issues on the planes.
> > > You are correct that crosstalk among traces will probably go up at
> > > a similar rate, but it is a matter of system design, which will pose a
> > > limitation first.
> > > If you hit the power/ground bounce limit first, and crosstalk is still
not
> > > harmful,
> > > a thinner power/ground laminate may help to reduce power/ground
bounce.
> > > If in the new stackup you still reference the same power plane, what
has
> > > changed is that the traces will be 'outside' of the power/ground
cavity,
> >not
> > > inside as before.  In this case only the ground reference plane for
the
> > > traces is
> > > what is further away from the power/ground plane pair.  If the
components
> > > on the board force you to have a large number of ground vias anyway,
you
> > > can get the sufficiently tight stitching between the ground planes
without
> > > extra
> > > expence.
> > >
> > >
> > > > b) At extreme high edge rate, the skin effect is limiting both the
> >signal
> > > > trace and the image current that flows on the reference plane, your
> > > infinity
> > > > argument doesn't exist. I can't answer an argument that cannot
exist.
> > >
> > > OK, let me rephrase the question that may be easier to answer.  Say
you
> > > have a working board, and you are satisfied with it.  It has a given
> >number
> > > of traces referencing the correct plane.  Say the transition times on
> >those
> > > traces are all around 1 nsec.  And lets suppose the power/gnd bounce
> > > is acceptable: not much lower than your target, but safely below your
> > > limit.  Suppose the only thing you change next is the silicon, and it
puts
> > > out
> > > 200psec transition times instead of 1nsec.  There is no other change
> > > on the board.
> > > The 200psec edges are 'slow' enough that within an inch radius we cant
> > > really
> > > expect any absorption due to skin effect, and the one inch radius
> > > approximately
> > > represents the distance the signals can go within 200psec.  So the
> > > question is: if you want to maintain about the same level of
power/ground
> > > bounce,
> > > would you change the plane structure; would you put the power/ground
> >planes
> > > closer, further apart, or leave them where they are?
> > >
> > > Regards,
> > > Istvan
> > >
> > >
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