[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc

  • From: steve weir <weirsp@xxxxxxxxxx>
  • To: nanda@xxxxxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 12 Feb 2004 09:30:05 -0800

Nanda, what you want to do is route orthogonally on layer 3 to layer 4.  If 
you have tandem ( parallel ) traces on the two layers, you can estimate the 
crosstalk based on the lateral spacing and lamda / 6 that results from the 
tandem length.

Steve.
At 10:02 PM 2/12/2004 +0530, Nanda wrote:
>Hi All,
>I have  a PCB Stackup as follows:
>LAYER 1 TOP
>LAYER 2 GND
>---- 4 mils spacing -----
>LAYER 3 SIG1 (trace width 4.5 mils)
>---- 7 mils spacing -----
>LAYER 4 SIG2  (trace width 4.5 mils)
>---- 4 mils spacing -----
>LAYER 5 GND
>LAYER 6 POWER1
>LAYER 7 POWER2
>LAYER 8 GND
>LAYER 9 SIG3
>LAYER10 SIG4
>LAYER11 GND
>LAYER12 BOTTOM
>
>Is the spacing of 7 mils between LAYER 3 SIG1 and LAYER 4 SIG2 is sufficient
>to avoid any cross talk?
>(the signals are orthogonal)
>
>regards,
>nand
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Istvan NOVAK
>Sent: Thursday, February 12, 2004 7:05 PM
>To: lenaw
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Stack up for EMI reduction, plane resonance and
>u-strip radiation etc etc
>
>
>MC,
>
>With all the recent postings I tried to show Chris that even if someone
>follows good engineering practices (referencing the correct plane),
>beyond a certain trace density and edge rate, it may make perfect sense
>to use thin power-ground laminates.  Of course you dont use them
>if you can avoid it by properly engineering the board.  And there is
>a gray area where the tradeoffs wont point very clearly one way or
>the other.
>
>I agree with the first half of your statement, but not completely with
>the second half of it.  If you change a G-S-PWR stackup portion to
>G-PWR-S-G, you dont have to change the spacing between S and
>PWR, so the trace inductance wrt PWR wont change (the total trace
>loop inductance wont change anyway if you use the same dielectric
>and same trace impedance).  The G-PWR inductance in the second
>stackup portion is so much smaller than the trace inductance, that it
>wont really change anything in that regard.
>
>Regards,
>
>Istvan
>
>
>----- Original Message -----
>From: "lenaw" <lenaw@xxxxxxxxx>
>To: <istvan.novak@xxxxxxxxxxxxxxxx>; "Chris Cheng"
><Chris.Cheng@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>Sent: Wednesday, February 11, 2004 11:22 PM
>Subject: Re: [SI-LIST] Re: Stack up for EMI reduction, plane resonance and
>u-strip radiation etc etc
>
>
> > Istvan:
> >            On (b) my opinion is that if you want to reduce the
>power/ground
> > bounce, you have to reduce the total effective inductance of the
> > power/ground planes ( assume you have no bond wire and use flip-chip
> > technology to connect the die to the package ) and it depends on what kind
> > of buffer technology you are using, signals on top of a pair of closely
> > coupled power/ground reference may not be the best solution because you
>need
> > the strong mutual inductance between the signal and power or ground planes
> > to reduce your total effective inductance during SSO. Just my 2cents.
> >
> >
> > Regards,
> > MC
> >
>
>
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