[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc

From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
To: "'Istvan NOVAK'" <istvan.novak@xxxxxxxxxxxxxxxx>,Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
Date: Wed, 11 Feb 2004 11:34:16 -0800

a) If your plane reference is so limited and crowed with highspeed traces
that it can not provide the effective capacitance, it will exhibit itself as
both xtalk and power/gnd bounce problem. The image current starts to overlap
each other and either add or subtract from each other. This is an observable
problem in most signal traces in organic packages. But I will turn the table
around and ask you, how could your fancy capacitor or thin core plane help
if they are electrically further from the reference planes ? It's like
challenging my Covertte saying "hey, I bet you can't drive this car at
300mph" while you are sitting on a pintle.
b) At extreme high edge rate, the skin effect is limiting both the signal
trace and the image current that flows on the reference plane, your infinity
argument doesn't exist. I can't answer an argument that cannot exist.

-----Original Message-----
From: Istvan NOVAK [mailto:istvan.novak@xxxxxxxxxxxxxxxx]
Sent: Wednesday, February 11, 2004 5:43 AM
To: Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Stack up for EMI reduction, plane resonance and
u-strip radiation etc etc 


Chris,

Comments below.

Regards,
Istvan



> 1) The difference is at the level. If you reference you 2GHz signal to a
12V
> plane with "functional" acceptable noise level for a 12V supply, say
+/-5%,
> you are asking for trouble. Does that mean you have to decouple the 12V
> power to the lowest highspeed noise level to maintain your acceptable
level
> ? Or do you simply move your signals to a more compatible voltage level
with
> proportionally lower noise level ?

No, my previous comments did not mean to imply that we reference the
'wrong' planes.  There is no disagreement there.  I simply asked how would
you change your plane capacitance requirement in a board if the same
'proper'
plane has to serve more traces in the same area.  Do you require more plane
capacitance or less?

> 2) No, higher speed edge signals requires less plane capacitance as the
> duration of the edge is shorter. And the proportion of the plane
capacitance
> area that is effective for the image current to flow back is also smaller.
> It works itself out. And the capacitance is controlled by the stack up of
> the impedance control.

So if we start out with a design that works properly, and traces (assume
single-ended
traces for the sake of argument) reference the proper plane, and you
change nothing else but make the signal edges gradually faster, do you say
that we can use less plane capacitance and therefore we can place the planes
further away?  Is this asymptotical, so that for infinitely fast edges we
need
no plane capacitance at all?

> 3) Same argument as above a), you will fail your "functional acceptable
> noise level" first before you can couple enough noise to harm your signals
> if you are referencing to a comptabile power level. If you insist on
running
> your highspeed signals on a 24v or 12v plane and running around claiming
you
> need to quiet those planes down to +/-100mV level, I just have nothing
more
> to say.
>

Yes, there is no disaghreement here.
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Follow-Ups:
- [SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc
  - From: Istvan NOVAK

[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc

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