[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc

From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
To: "'Istvan NOVAK'" <istvan.novak@xxxxxxxxxxxxxxxx>,Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
Date: Thu, 12 Feb 2004 13:13:32 -0800
No,no,no. We are not in agreement. Especially you haven't answer my question
:
"how could your fancy capacitor or thin core plane help if they are
electrically further from the reference planes ? "

First of all, you can't get into the power and ground bounce issue with the
reference planes without getting into  crosstalk problem. Afterall, it is
the constructive overlapping of the image current that creates the
power/ground bounce problem in the first place.

Now let's think about what do you need to do to bring in the thin core
decoupling plane to relief the problem. You first need to drill vias to
bring the image current from the reference power plane to the other side of
the power plane that has the thin core capacitor. The current then has to AC
coupled to the ground plane through the thin core and then come down to the
ground reference plane with additional ground vias. This is not a low
impedance path as compared with direct plane coupling and the vias has to be
numerous and very close to the signal traces to be effective. Here comes the
problem, if your signal traces are so close that the image current starts to
overlap on the reference already, WHERE ON EARTH DO YOU FIND THE SPACE TO
DRILL THE NECESSARY VIAS ?
Like I said before these power/gnd bounce problem on signal trace crowding
is an observable problem on highspeed high density package. I have done
enough of these packaging analysis to convince myself your trade-off point
does not exist. i.e. Either your traces will be so spaced out that vias can
be drilled near but then their image current don't overlap each other
significantly on the reference plane to create power/gnd bounce problem OR
they will be so tight and close that you can't drill your via to bring in
your thin core relief current anyways. 

And for the last time to answer your last question. The spacing between the
signal/power/gnd planes are dictated by the impedance control parameters. It
is not dependent on the edge rate of the signals.

What I am disappointed and alarmed is all these discussions/arguments has
been repeated over and over in this forum and if you go back to the archive
a few years back, there was a flare up with exactly the same argument and I
have pointed out exactly the same problem. Did anything changed since then ?
I certain have not changed your mind and neither have I so what's the point
of continuing this discussion ?


-----Original Message-----
From: Istvan NOVAK [mailto:istvan.novak@xxxxxxxxxxxxxxxx]
Sent: Wednesday, February 11, 2004 7:59 PM
To: Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Stack up for EMI reduction, plane resonance and
u-strip radiation etc etc 


Chris,

> a) If your plane reference is so limited and crowed with highspeed traces
> that it can not provide the effective capacitance, it will exhibit itself
as
> both xtalk and power/gnd bounce problem. The image current starts to
overlap
> each other and either add or subtract from each other. This is an
observable
> problem in most signal traces in organic packages. But I will turn the
table
> around and ask you, how could your fancy capacitor or thin core plane help
> if they are electrically further from the reference planes ? It's like
> challenging my Covertte saying "hey, I bet you can't drive this car at
> 300mph" while you are sitting on a pintle.

So I think we are in agreement here that if trace density is increases,
beyond
a certain point we will have power/ground bounce issues on the planes.
You are correct that crosstalk among traces will probably go up at
a similar rate, but it is a matter of system design, which will pose a
limitation first.
If you hit the power/ground bounce limit first, and crosstalk is still not
harmful,
a thinner power/ground laminate may help to reduce power/ground bounce.
If in the new stackup you still reference the same power plane, what has
changed is that the traces will be 'outside' of the power/ground cavity, not
inside as before.  In this case only the ground reference plane for the
traces is
what is further away from the power/ground plane pair.  If the components
on the board force you to have a large number of ground vias anyway, you
can get the sufficiently tight stitching between the ground planes without
extra
expence.


> b) At extreme high edge rate, the skin effect is limiting both the signal
> trace and the image current that flows on the reference plane, your
infinity
> argument doesn't exist. I can't answer an argument that cannot exist.

OK, let me rephrase the question that may be easier to answer.  Say you
have a working board, and you are satisfied with it.  It has a given number
of traces referencing the correct plane.  Say the transition times on those
traces are all around 1 nsec.  And lets suppose the power/gnd bounce
is acceptable: not much lower than your target, but safely below your
limit.  Suppose the only thing you change next is the silicon, and it puts
out
200psec transition times instead of 1nsec.  There is no other change
on the board.
The 200psec edges are 'slow' enough that within an inch radius we cant
really
expect any absorption due to skin effect, and the one inch radius
approximately
represents the distance the signals can go within 200psec.  So the
question is: if you want to maintain about the same level of power/ground
bounce,
would you change the plane structure; would you put the power/ground planes
closer, further apart, or leave them where they are?

Regards,
Istvan

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Follow-Ups:
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  - From: Istvan NOVAK
[SI-LIST] Re: Stack up for EMI reduction, plane resonance and u-strip radiation etc etc

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