[SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <Charles.Grasso@xxxxxxxxxxxx>, <weirsp@xxxxxxxxxx>,<hassan@xxxxxxxx>
- Date: Tue, 13 Jan 2004 07:53:40 -0800
As a added note from the EDA vendor side of this. IBIS has long had place
holders for data
that would help with the SI and POWER package simulation. Such things as a
mapping between
power pins and drivers. But even this simple level of data has very rarely
(if ever) been provided
by the IC manufacturer.
Several tools are either on the market or have been on the market that can
help with this kind of simulation but
without the data for the IC's there isn't much you can do.
One might also argue (and I believe several on this thread have) that even
if you find a problem on the IC through simulation, you can't fix it if you
are the board designer.
cheers
jon
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Grasso, Charles
Sent: Tuesday, January 13, 2004 6:42 AM
To: 'weirsp@xxxxxxxxxx'; 'hassan@xxxxxxxx'
Cc: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling
Guide
Steves comment is worth repeating:
"Scott and Martin both point out the dearth of adequate information on the
Si/package combination leaves us guessing as to what is needed at the board
level to care for and feed a given device"
Which begs the question: What information SHOULD be provided by the
die/package manufacturer to allow for a proper PDS design?
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]
Sent: Tuesday, January 13, 2004 12:12 AM
To: hassan@xxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide
Hassan, with all due respect, I believe you are taking Chris' comments out
of context. If you follow his earlier comments, I think you will find that
he is very clear on the need to design the entire power system. Chris
emphasizes that a lot of people are focused on trying to fix at the PWB
level problems that are either in the Si/package, or not really there at
all.
Scott and Martin both point out the dearth of adequate information on the
Si/package combination leaves us guessing as to what is needed at the board
level to care for and feed a given device. It is very suboptimal to have
to guess at, or create characterization fixtures for IC's that the mfgs.
darn well better have designed and validated properly. Yet that data is
not getting to the integrators who the mfg's want to sell their IC's to.
As a tool vendor, this situation is probably an opportunity for you to sell
tools to the chip mfg's that will allow them to readily and cost
effectively provide the data that we as integrators sorely need.
Steve.
At 01:32 AM 1/13/2004 -0500, Hassan O. Ali wrote:
>I'm afraid this discussion is getting into over-generalization and
>over-simplification of the problem in question.
>
> Chris Cheng says:
>
> > if you have
> > poorly design chip and package, you need a hell of a lot of decoupling
and
> > BC planes to fix it at the system level
>
>That is one example of generalization. Not every device-level power
>distribution flaw can be solved at the board level. As a matter of fact,
>many papers/documents I've read so far on this subject do clearly
>indicate the limitations of the PDS at the board level. The board-level
>PDS design only focuses on providing the power quality at the device's
>power pins/balls.
>
>Contrary to what Chris Cheng wants us to believe, you cannot
>realistically meet all power distribution requirements by focusing only
>on the device level. For one thing, the power comes from outside the
>device, right? How can you then ignore the path through which the power
>goes through before entering the device! Will the power delivered
>through two backplane connectors and a 60-in backplane trace be of the
>same quality as that delivered through an inch of fat PCB trace?
>Certainly not.
>
>Hassan.
>
>
>
>Scott McMorrow wrote:
>
> >Chris is correct.
> >
> >This was exactly my point previously. Without knowledge of the silicon
> >and package power distribution it is impossible to perform an analysis
> >of the entire power distribution system. But a well designed piece of
> >silicon and package will require very little support from the PCB.
> >
> >scott
> >
> >
> >Chris Cheng wrote:
> >
> >
> >
> >>I disagree. No one should be surprised. I have said many times, there
is
> >>never a need for fancy decoupling scheme on PCB for properly design
> >>processor and package. Nothing should be need for >100MHz core noise and
> >>signal return is a case of reference plane management (does that sound
like
> >>a broken record yet ?)
> >>
> >>
> >>
>
>
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