[SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide

  • From: Mark Alexander <mark.alexander@xxxxxxxxxx>
  • To: steve weir <weirsp@xxxxxxxxxx>
  • Date: Mon, 05 Jan 2004 18:43:54 -0700

Steve,
Thank you for the comments -- this sort of criticism is always helpful.

In defense of the strategies we advocate in this appnote, there are many 
ways to skin a cat.  I'm presenting methods that we have seen repeatedly 
to work well for FPGA designs.  The aim was not to write a flawless 
treatise on the art -- it was to put forth a guide that any PCB designer 
can use with success. 

The items you've listed below are valid points.  I could go through them 
and tell you why I decided to present the information that way, but 
that's not the point.  Many simplifications were made in order to get 
the basic points across.  I encourage people to take this appnote for 
what it's worth -- a fairly comprehensive set of guidelines that we know 
will work with our devices. 

I will take into consideration what you've said below, in particular the 
points on X2Y caps that we haven't investigated in detail yet.  I'll 
also put some notes inline below. 

Regards,
mark


steve weir wrote:

> Mark,
>
> I have a few other comments on that appnote:
>
> Figure 6 shows the induction loop only including the capacitor down to 
> the power layer.  This needs to be changed to show the whole loop of 
> interest is effectively from the capacitor to the far plane.  The 
> interplane capacitance density is nothing like that of the decoupling 
> cap and cannot support the field.

Point taken that the loop shown in figure 6 is not the whole story.  
However as to the capacitance density of BC being able to support the 
field, I think the jury is out on this point.

> I am not happy with the characterization of capacitor effective 
> frequency.  

I am.

> I think that this is where the note is the weakest as I think it lends 
> itself to the idea that a broad range of closely spaced capacitor 
> values must be used.  That is one strategy that can work and is 
> promoted by both UltraCAD, and the work done by SUN.  But, it is not 
> the only solution.  

Agreed.  As for now, it's a valid solution and we still stand by it.  
Ceramic caps lend themselves to decoupling.  They also have fairly 
high-Q, which can bite you if you're not careful.  This is why we 
emphasized the simple first-order stuff.

> As traditional geometry capacitors become less relevant for 
> decoupling, it will become less applicable.

True, but we're not there yet.  There's plenty of mileage left in 
traditional discretes.

> You should update your description of the effective resonant frequency 
> to include ESR.  With many capacitors the Q is so high that ESR does 
> not shift the damped natural frequency significantly.  But, with 
> others like X2Ys, it does.
>
> Rather than using frequency as the basis for capacitor placement, I 
> suggest changing to time domain current demand and inductance.  

Agreed.  However it's tough to justify this level of analysis in an 
appnote of this scope.

> It is readily shown how little even a lot of BC supports large 
> switching currents.  

Where?  It depends which analysis you look at and the approximations you 
assume.  I'll bet that on this list we could find equal numbers of 
successful designers in each camp.

> While I liked your discussion of decoupling placement radius in 
> general, I think your propagation constants are too fast leading to 
> liberal radii.  Power planes behave as striplines and will be more 
> like 180 to 220 ps/in than 130 ps /in of a surface microstrip.

See John Zasio's discussion in Right The First Time.  What do you think 
of it?

> Capacitors values spaced over decades is largely a myth that has been 
> debunked.  

By who?  Please refer me to relevant papers.

> Mounted SRF's vary by about 3:1 with such an arrangement, leading to 
> significant antiresonance at about 1.7X the lower SRF.  

Which is why we recommend the use of multiple values of these high-Q 
elements (ceramic caps).

> UltraCAD and SUN have both shown that spacing values by no more than 
> 2:1 yields a PDS impedance using far fewer parts than spacing on 
> decades.  

??  I'm missing something... doesn't that mean their networks would have 
more values, not less?

> I am doing some work now on further reducing this with X2Y caps.  My 
> personal view on decoupling HF is that the first approximation is from 
> raw vias.  The number of capacitors falls out from the number of vias, 
> and the type of capacitor technology selected.

I agree with you here.  I think this is where it's going.  Again, we'll 
be a step or two behind in what we publish as an appnote.  We can't 
afford to publically recommend methods that aren't fully understood.

>
>
>
> Regards,
>
>
> Steve.
>
>
>
>
>
> Steve
> At 05:28 PM 1/5/2004 -0700, Mark Alexander wrote:
>
>> Steve, Tegan,
>>
>> That appnote is one of mine, and you're correct -- these are 
>> representative numbers, not hard values.  When this was written 2 
>> years ago, very few people were making measurements with accuracy 
>> that could distinguish between a 500pH mouting and a 650pH mounting.  
>> That's a bad excuse -- now that this information is more commonplace, 
>> it looks like I've got some updating to do, even if only to put some 
>> bounds on the accuracy of the numbers presented.
>>
>> John Zasio's section of Lee's book is a good place to go for numbers, 
>> as are the papers on Istvan Novak's webpage.  In particular, see the 
>> DesignCon 2003 TecForum paper and the EPEP 2003 paper.
>>
>> -mark
>>
>>
>>
>> steve weir wrote:
>>
>>>
>>>Tegan,  the numbers in that application note are
>>>representative, and not 
>>>hard values.  The smaller values in-particular depend greatly on the 
>>>distance to the planes.  I think they are a little optimistic with
>>>their 
>>>shown 600 and 500 pH configurations.  My experience is that those
>>>would run 
>>>more like 800pH and 650pH respectively.  But, again, that depends on
>>>the 
>>>height above the planes.
>>>
>>>I also would not use their configuration (d).  For a four via
>>>connection, 
>>>placing the vias on either side of the long axis of the pad results in 
>>>lower inductance than outboard of the long axis of a normal geometry 
>>>capacitor.  That doesn't matter too much when using a crummy
>>>capacitor with 
>>>800-900nH of package inductance, but it can make a big difference if you 
>>>use reverse geometry, or X2Y caps.
>>>
>>>0603's 750pH package
>>>0306's 200pH package
>>>0603 X2Y 120pH package
>>>
>>>We can range from single via mounts of 800pH to three via mounts of 300pH 
>>>to get resulting inductances of:
>>>
>>>420pH X2Y three via to 1550pH 0603 with single vias.  In either
>>>case, to 
>>>get to a given target impedance we are driven to drill a commensurate 
>>>number of via holes, and then add caps.  The worst choice is
>>>traditional 
>>>caps, where we need to drill about 25% more holes and need almost 4X as 
>>>many capacitors total versus using X2Ys.  Reverse geometry caps can
>>>just 
>>>about get away with a like number of holes as X2Ys, but need about 25%
>>>more 
>>>caps than X2Ys due to the higher package inductance.
>>>
>>>Condemned was only a reference to the effort needed to find and collect
>>>the 
>>>papers.  It would be great if there was a single comprehensive
>>>reference 
>>>for this subject, but I don't know of one.
>>>
>>>Steve.
>>>At 03:27 PM 1/5/2004 -0700, Tegan Campbell wrote:
>>> 
>>>      
>>>
>>>>
>>>>All,
>>>>There is a Xilinx app note on their site(Xapp 623) that they talk about
>>>>different mounting inductances of capacitors but give no source for
>>>>their
>>>>information.  I noticed that Lee Ritchey said in an earlier email he
>>>>had
>>>>data to back up modeled inductances of different mounting structures.
>>>>Does anyone with the knowledge want to take the time to look at the
>>>>paper(figure 5) and provide data that agrees or disagrees with their
>>>>assumptions?
>>>>
>>>>And Steve, "condemned" might be a bad choice of words in the
>>>>paragraph
>>>>below.  I found some VERY useful information and perspectives in
>>>>those
>>>>papers.
>>>>
>>>>Tegan
>>>>
>>>>
>>>>Hassan,
>>>>
>>>>I don't know of one place you are going to find all of that.  There
>>>>are a
>>>>series of worthwhile chapters in Lee's book:  "Right the 
>>>>First
>>>>Time".  There is also some coverage in Dr. Johnson's
>>>>book:  "High Speed
>>>>Digital Design", and Hall's book as well.  Beyond those titles,
>>>>I think you
>>>>are condemned to plucking out papers such as many written by the folks
>>>>at
>>>>SUN, and others.
>>>>
>>>>Steve.
>>>>At 04:52 PM 1/5/2004 -0500, Hassan O. Ali wrote:
>>>>   
>>>>        
>>>>
>>>>>
>>>>>Could anyone recommend a definitive design guide for board-level
>>>>>power
>>>>>distribution,
>>>>>filtering, and decoupling suitable for PCB's with multi-voltage,
>>>>>multi-gigabit, mixed-
>>>>>signal devices?
>>>>>
>>>>>Thanks.
>>>>>
>>>>>Hassan.
>>>>>     
>>>>>          
>>>>>
>>>>
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