[SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide

  • From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
  • To: "'cgrassosprint1@xxxxxxxxxxxxx'" <cgrassosprint1@xxxxxxxxxxxxx>,martin@xxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Mon, 12 Jan 2004 17:58:19 -0800

I disagree.  No one should be surprised. I have said many times, there is
never a need for fancy decoupling scheme on PCB for properly design
processor and package. Nothing should be need for >100MHz core noise and
signal return is a case of reference plane management (does that sound like
a broken record yet ?)

Call me cynical but most of the so call power distribution papers, book
authors never have a complete picture of the power distribution scheme. They
either built some fancy plane model of a pcb or some complicated package
model and "discover" these crazy resonance here or there and proclaimed
"there, we've got a problem on this package or pcb, I see this huge peak at
xxxM or G/Hz". What they don't know is the effect of on die power grid and
decoupling effect which will significantly change the resonance pattern and
frequencies. Anyone who really have done a complete analysis including on
die power grid will be bounded by their own company gag rule to not telling
you what they are. I always call that "core competency". Either you know it
or you don't. Couple this with overly eager PCB vendor who are pushing BC or
cap vendors trying to sell you expensive caps or even CAD vendor who want to
get your PO for that "plane analyzer tool that can hunt for xxxMHz resonance
in your PCB", you've got an urban legend that feeds a whole industry of
consultants, vendor and tools that provide a solution that is looking for a
problem.

I do have to agree, as Steve Weir pointed out previously, if you have a
poorly design chip and package, you need a hell of a lot of decoupling and
BC planes to fix it at the system level. But two wrong does not make one
right in my book.

BTW, I ran couple of those power analysis groups in a server and a PC
processor company. I hope you will trust what I am saying.

-----Original Message-----
From: Charles Grasso [mailto:cgrassosprint1@xxxxxxxxxxxxx]
Sent: Monday, January 12, 2004 6:20 PM
To: martin@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling
Guide


Thanks for the info Martin. I learn more from things that work - but
shouldn't.!!

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Martin Euredjian
Sent: Monday, January 12, 2004 5:08 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling
Guide


So... I just got one of the new Intel D875PBZ motherboards (3.6GHz, 800MHz
FSB, etc.).  In looking at it, one of the things that caught my eye
immediatlely was wasn't there.  I was expecting lots of decoupling
capacitors, particularly surrounding certain chips.  To my surprise, the
design has absolutely no components on the bottom and an (appartent) handful
of decouplers on the top layer.

With all the talk and controversy on this forum, application notes, papers
and books describing gargantuan capacitor trees as a requirement for good
signal integrity, reduce RFI, etc. it's always been a surprise to run across
product after product that does not seem to fit the proposed model very
well.  Am I missing something fundamental here?


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
eCinema Systems, Inc.
voice: 661-305-9320
fax: 661-775-4876
martin@xxxxxxxxxxxxxx
ecinema@xxxxxxxx
www.ecinemasys.com




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