[SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide]
- From: "zhiping yang" <zhiping@xxxxxxxxx>
- To: <Chris.Cheng@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 Jan 2004 17:55:15 -0800
Hi Chris,
Thank you for sharing your thoughts and Very good points about the power
integrity.
One comment about your "total system approach". Technically speaking, it is
best to put the equal amount of efforts on the die, package and PCB power
distribution since they are equally important in the complete power delivery
system. More important, the PCB COULD NOT fix the problems with the die and
package power delivery systems in some cases.
In the real word, when cost and $$ is involved, the trade-offes must be
made, so the design may not be optimized in technical side. For example,
due to the high cost of die size increase and package limitations, it may be
more cost effective by shifting the power integrity problem to the PCB level
at a certain degree. This may require using BC or more decoupling caps on
the board, but it could still be cost effective from the "total system"
point view.
This is my $0.02 input. Thanks.
Zhiping
----- Original Message -----
From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, January 13, 2004 12:55 PM
Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide]
> Ok, I want to start this thread again free of attachments.
> There is no need to form another benchmark committee or develop some
> industrial standard tool to address the high speed power distribution
> issues.
> What I've been preaching is just plain common sense and what I call "total
> system approach" where you attack the problem at die, package, PCB and
power
> supply level. You simply cannot focus on just one section of the chain of
> distribution and expect it to do all for you.
> Maybe I start off as too sarcastic and lead you to believe finger pointing
> is the only way to solve this problem. It is not. And if you buy into my
> "total system approach", you should also look into its corollary :
>
> A certain component that cause system problem usually mean there is some
> problem internal to the chip also.
>
> If you see huge EMI radiation coming out of a chip, it probably also
suffers
> a large core noise on die or some sort of SSO noise. For every poor system
> engineer trying to quiet down the EMI noise coming out of a chip, there is
> another chip designer scratching his head trying to suppress the core
noise
> on his silicon. We are not working in an island in the middle of nowhere.
> Every thing we do on chip has direct impact on the system and vice versa.
> The sad thing is there are only a few people or companies that have the
> luxury of having done a complete analysis through the entire path. And
> chances are they will lock up this knowledge and treat it as their own
"core
> competency". I am sorry to sound cut throat but that's the way the big
boys
> play. There is a reason why you go with a company that sell a 100 million
> pieces a year instead of a few thousands. They are the big boys and they
> (although not always) tend to know what they are doing. Or at least they
> have enough volume to see every possible problem that exist under the sun
> and have enough resources to spend men years to analyze and solve them.
> Every power analysis group I ran in those company takes men years to
> complete. And every bit of the techniques and methodology are in house and
> proprietary. All I can say is tools are never a problem, I did most of
them
> with plain old SPICE and freely available FastHenry. It is the insight
into
> every detail of the components like on die power grids, package structures
> etc that really make or break the design. Unfortunately, you cannot learn
or
> gain those insights simply by joining the "Si-list". This is just a simple
> way of natural selection. If you find a chip that cause you noise problem
in
> a system, you either make the vendor fix it or you switch vendor. I don't
> feel sorry for the semiconductor house that have a lousy design and loose
> their business. On the other hand, a chip house that does its homework and
> has a clean design deserves to win your business no matter they are a
> semi-monopoly or charge you an arm and a leg. They pay their dues and save
> your from system level trouble down the road.
> I have seen quite a few big shots in chip houses that told me "men, I
would
> have given you a few millions to turn back the clock and fix our problem
> before we learn it through the hard way." Believe me, this is not just a
> system company or chip company issue. They both suffer the same.
> There are Yugos and there are Corvettes, you can't buy a Yugo and take it
to
> the race track and then complain "hey don't blame me, I have a lousy car".
> Its your choice to pick the right component.
> If there is anything to learn here, it is to take SI and packaging issues
> seriously in your component selection. Don't just let the system architect
> or board manager dictate what chip to use simply because it cost a few
buck
> less or have this feature extra. Ask questions, look into data, review
their
> package to make sure it also make sense in SI first. Assert yourself in
the
> selection process. If you think there is not enough signal to ground pin
> ratio, raise you hand and ask why. Don't just sit at the corner and tell
> your system manager "I think it will work". That's what we got paid for.
Not
> just putting in band-aids as an after the fact thing. We also got paid to
> prevent bad things from happening in the first place.
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