[SI-LIST] Re: 6 layers stackup
- From: "Ray Anderson" <ray.anderson@xxxxxxxxxx>
- To: "Saoer Sinaga" <saoer.sinaga@xxxxxxxxx>
- Date: Wed, 23 Apr 2008 14:00:51 -0700
One motivation for keeping the P and G planes next to each other is to
minimize the power distribution network loop inductance and hence
minimize SSO. (the inductance is proportional to the plane separation)
-Ray
Xilinx Inc.
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Saoer Sinaga
> Sent: Wednesday, April 23, 2008 1:31 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: 6 layers stackup
>=20
> Dear all,
> May I know the reason why people would generally use S1 S2 G P S3 S4
> configuration for six-layer stackup? Why not S1 S2 P G S3 S4?
> Thanks.
>=20
> regards,
> Saoer
>=20
> On Wed, Feb 20, 2008 at 11:17 PM, Fernando Yuitiro Mori
> <mori@xxxxxxxxxxxxx>
> wrote:
>=20
> > Hi,
> > I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I need the
4
> > layer with 60 ohms, so there are some problem if I use S1 G S2 S3 P
S4?
> >
> > Regards,
> >
> > Fernando Mori
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