[SI-LIST] Re: 6 layers stackup

Dave, Fernando my $0.02 on 4/6 layer stack-ups with a single symmetric 
power cavity:

1) The Z-axis inductance seen at the IC solder pads to the power cavity 
is pretty much fixed by:

a. The total thickness of the PCB.
b. The pin-out of the IC.
c. The via drill diameter.

2) Similarly the Z-axis inductance seen between the bypass caps and the 
power cavity is fixed by:

a. The total thickness of the PCB.
b. The type of bypass capacitors used.
c. The via pattern used w/ the bypass caps.
d. The via drill diameter.
e. The areal density of the bypass caps used.

b/c/d Determine the mounted inductance of each cap.  X2Y(r)'s and 
IDC(r)'s yield the best results.  In all cases the via pattern used 
makes a big difference in the number of caps used and the behavior at 
parallel resonance.  In my mind it is a lot better to floor plan bypass 
caps w/ optimal via patterns up front, than to have the PCB designer try 
to fit them in later.

3) As the power cavity is made thinner, six notable things happen:

a. The horizontal spreading inductance of the planes falls.  The 
extremes for six layer 0.062" stack-ups can be almost 10:1 going from a 
4 mil to a 38 mil power core.
b. The high frequency impedance of the power system comes down.  On the 
bad side one will be in PCB wave effects at lower frequencies.  Detuning 
w/ discretes takes about the same number of parts independent of the 
cavity thickness.  Tolerances are more forgiving for the thinner cavity.
c. The parallel resonant frequency of the power system comes down as the 
square root of the power cavity thickness.  Typical resonant frequencies 
typically vary over a 300MHz to 1.5GHz range depending on bypass scheme 
over the 4mil to 38mil cavity thicknesses.
d. The Q of the parallel resonance goes up.  On the good side, higher Qs 
are generally easier to detune.   The bad side is that the natural 
magnitude of Zpeak is fairly independent of the cavity thickness, now it 
is much more likely to be where there is more signal energy.  The moral 
here is:  detune the resonance.
e. Above and below the resonant frequency noise attenuation improves.
f. The asymmetry between outer and inner routing layers in a 6 layer 
stack-up become more pronounced and routing density can suffer 
severely.  Maintaining 50Ohms and/or acceptable cross talk values on 
outer layers more than about 10 mils from an image plane demands some 
rather wide traces and routing pitches.

4) An S1 G S2 S3 P S4 stack-up works best when the highest speed signals 
can be broken out and routed completely on S1.  Otherwise S1 P S2 S3 G 
S4 is usually better breaking out high speed signals on layer S4 first 
and layer S3 second, minimizing via stubs.  In either case prioritizing 
the traces with the most high speed energy to the routing layer(s) 
adjacent an image plane connected to the dominant coupling rail in the 
IC will help reduce demands on the PDN.  That rail is usually ground.

Best Regards,

Steve.


DAVID CUTHBERT wrote:
> Fernando,
> The S1 S2 G P S3 S4 stackup can provide excellent power plane performance at
> the expense of S1 and S4. Routing S1 and S4 mostly at right angles to S2 and
> S3 can greatly reduce the crosstalk. And using narrow traces to maintain the
> Z0 of S1 and S4 will take care of the Z0.
>
> I often use S1 G S2 -  S3 P S4 for 6-layer boards. The signal traces are
> nicely isolated with a 62 mil board having spacing like so:
> 10 mils, 5 mils, 22 mils, 5 mils, 10 mils. The tradeoff is that the power
> plane Z0 is about 2X that of a board having 10 mils between each layer. The
> power plane Z0 is still quite low with an inductance of about 200 pH per
> square. Contrast this to an S1-G via inductance of about 300 pH and the
> plane Z does not dominate things.
>
>      Dave Cuthbert
>      NARTE Certified EMC Engineer
>      Consulting, SI, EMC, power electronics, analog of all kinds
>
>
> On Wed, Feb 20, 2008 at 2:17 PM, Fernando Yuitiro Mori <mori@xxxxxxxxxxxxx>
> wrote:
>
>   
>> Hi,
>> I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I need the 4
>> layer with 60 ohms, so there are some problem if I use S1 G S2 S3 P S4?
>>
>> Regards,
>>
>> Fernando Mori
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