[SI-LIST] Re: 6 layers stackup
- From: steve weir <weirsi@xxxxxxxxxx>
- To: QU Perry <Perry.Qu@xxxxxxxxxxxxxxxxxx>
- Date: Wed, 27 Feb 2008 09:19:06 -0800
Perry, where one mounts capacitors influences modal resonances. The
extreme of this is a single capacitor mounted anywhere, versus an array
of capacitors distributed over the PCB area. As you note, the frequency
of modal resonances also depend on where one injects energy into the
cavity. For a rectangular cavity the results for an injection point
dead center are very different than the center of one edge, or any of
the corners.
To understand why with distributed capacitors the parallel resonance is
closely determined by the area / unit inductance of the bypass network
and capacitance per unit area of the planes, we can return to the cell
model. If we transform each transmission line into an RLCG equivalent,
we end up with a bed spring model that places a capacitance at the
center of R-L "arms". For simplicity we can scale the cell size to
match the distribution density of the bypass caps, or some integer
multiple of that. Now, what we have is a parallel resonant tank that
consists of the capacitance in the cell, and for R-L, the ESL and ESR of
the cap ( or fraction thereof corresponding to the cell ), and the
spreading resistance and inductance of the cell. As long as the
capacitors are spread fairly evenly, the parallel resonance of the board
plus bypass caps is relatively fixed.
If we use just one cap the situation changes in that the spreading
inductance between the capacitor and the distributed capacitance of the
planes depends on where the cap is relative to the center of the PCB.
At the center of the PCB, the bypass cap will see about half the
spreading inductance to the distributed plate capacitance of the cavity
as it will mounted at one edge. If we have a thick cavity with
spreading inductance that is significant over its extents compared to
the capacitor mounted ESL, then we will see a visible shift in the PRF
as we move the one bypass cap from one edge of the board to the center.
In the limit where the cavity looks like a trace that adds negligible
capacitance we have just added the trace inductance of the bypass cap.
Conversely, if the plane spreading inductance is low compared to the
capacitor mounted inductance, then the PRF is relatively independent of
the capacitor position.
Best Regards,
Steve.
QU Perry wrote:
> Scott/Steve,
>
> I did some spice simulation a few years ago to calculate power plane
> impedance on plane pairs following the paper from Agilent/Sun
> Microsystem, i.e., dividing the planes into small cells and model each
> cell with transmission line elements. What I observed:
>
> 1. half-wave resonance frequency predicted for the power/gnd pair
> assuming a 2D cavity (Z is much smaller than X/Y) matches very well
> with the spice simulation results;
>
> 2. Depending on the measurement location on that plane, you will get
> different modes and resonance pattern comparing a location at corner
> vs. center of the plane (number of modes to be excited);
>
> 3. The first null in the self-impedance curve also varies
> significantly depending on where we measure;
>
> That makes me believe that if we mount capacitor with certain mounting
> inductance, it will induce different anti-resonance at different
> measurement points, thus PRF will vary also depending on your
> measurement points on that plane.
>
> Regards
>
> Perry
>
> =======================================
>
> Perry Qu
>
> Design & Qualification, Alcatel-Lucent Canada Inc.
>
> 600 March Road, Ottawa ON, K2K 2E6, Canada
>
> DID: 613-7846720 Fax: 613-5993642
>
> Email: perry.qu@xxxxxxxxxxxxxxxxxx
>
> =======================================
>
>
>
> ------------------------------------------------------------------------
> *From:* Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> *Sent:* Monday, February 25, 2008 3:30 PM
> *To:* QU Perry
> *Cc:* steve weir; si-list@xxxxxxxxxxxxx
> *Subject:* Re: [!! SPAM] [SI-LIST] Re: 6 layers stackup
>
> Perry
>
> Plane parallel resonance is proportional to 1/sqrt(LC). Where L
> is the inductance of the bypass capacitors and C is the
> capacitance of the plane. C is proportional to Er, plane area,
> and plane thickness. And L is proportional to the mounted
> inductance of the bypass capacitors.
>
> If we do not change material, then Er is constant. PRF is then
> controlled by the plane area, thickness, capacitor type, capacitor
> placement, and capacitor mounting attach. Lets assume an 0.063"
> board that is 12"x12".
>
> The largest plane we can have is 12"x12", or 144 sq in.
> The smallest fill area plane we can have around a large BGA, is
> about 2"x 2", or 4 sq in.
> This is a 36:1 ratio, which will shift PRF by a factor of 6:1
>
> Lets say the thickest possible power/ground plane pair is 52 mils,
> and the thinnest is 4 mils.
> Our ratio is 13:1, which will shift PRF by a factor of 3.6:1
>
> The mounted inductance of a capacitor is:
>
> Lmount = Lcap + Lvia + Lspread
>
> For well-mounted 0402 capacitors with 4 mil ground/power plane
> separation as close to the capacitor as possible, Lcap + Lvia is
> about 450 pH.
>
> The radial spreading inductance for these capacitors placed on a
> 2" radius from a chip where the power balls are placed on the
> average at a 1" radius from the center is
>
> Lspread = 5pH/mil x ln(R2/R1)
> Lspread = 5pH/mil x ln(2000/1000)
> Lspread = 3.47 pH/mil power/ground plane dielectric thickness
>
> In our hypothetical case, our min to max spreading inductance is:
>
> Lspread = 14 pH to 180 pH
>
> At the same time, as the planes are moved further down in the
> stack from the capacitors there is additional inductance due to
> additional via reach. Depending on the via size and spacing, this
> is around 10pH to 20pH per mil inside the PCB cavity. For our case
> Lvia can range from:
>
> Lvia = 0pH to 960 pH
>
> Lmount = Lcap + Lvia + Lspread = 464pH to 1590pH
> For a range of 3.4:1, for a total PRF shift of 1.85:1
>
> If we calculate total PRF shift due to thickness and plane
> location changes:
>
> PRF shift(due to plane thickness and location to ) = 6.66:1
> From above:
> PRF shift(due to plane area) = 6:1
>
> PRF can change due to area of the planes, the separation of the
> planes, and the location of the planes w.r.t. where the bypass
> capacitors are mounted. Whether you place the bypass capacitors
> on the component side, outside the part periphery, or on the
> opposite side, in the component via pad field, does not change the
> above PRF ratio calculations.
>
>
> Scott
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
> Teraspeed® is the registered service mark of
> Teraspeed Consulting Group LLC
>
>
>
>
> QU Perry wrote:
>> Steve:
>>
>> My understanding on the impact of thinner power cavity is mainly the
>> reduction of spread inductance, such that any added benefit of IDC/X2Y
>> placed at the peripheral of BGA will not be compromised by the planes.
>> In most applications however, we rely heavily on the decoupling caps
>> (0402) directly placed underneath BGAs, and in those cases, I would
>> think thickness of power cavity is not important as the total inductance
>> looking into PCB from BGA pads to the planes and to the decoupling caps
>> don't change. Your thoughts ?
>>
>> I'm also not clear when you say parallel resonance frequency is driven
>> by thickness. Comparing Z dimension vs. X/Y for a normal power plane/PCB
>> thickness, I would say the resonance frequency is mainly determined by
>> how big the plane is not how thick the cavity ?
>>
>> Thanks
>>
>> Perry
>>
>>
>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=20
>>
>> Perry Qu=20
>>
>> Design & Qualification, Alcatel-Lucent Canada Inc.
>>
>> 600 March Road, Ottawa ON, K2K 2E6, Canada=20
>>
>> DID: 613-7846720 Fax: 613-5993642=20
>>
>> Email: perry.qu@xxxxxxxxxxxxxxxxxx=20
>>
>>
>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=20
>>
>> =20
>>
>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx=20
>>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
>>> Sent: Saturday, February 23, 2008 6:44 PM
>>> To: DAVID CUTHBERT
>>> Cc: Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
>>> Subject: [SI-LIST] Re: 6 layers stackup
>>> =20
>>> Dave, Fernando my $0.02 on 4/6 layer stack-ups with a single=20
>>> symmetric power cavity:
>>> =20
>>> 1) The Z-axis inductance seen at the IC solder pads to the=20
>>> power cavity is pretty much fixed by:
>>> =20
>>> a. The total thickness of the PCB.
>>> b. The pin-out of the IC.
>>> c. The via drill diameter.
>>> =20
>>> 2) Similarly the Z-axis inductance seen between the bypass=20
>>> caps and the power cavity is fixed by:
>>> =20
>>> a. The total thickness of the PCB.
>>> b. The type of bypass capacitors used.
>>> c. The via pattern used w/ the bypass caps.
>>> d. The via drill diameter.
>>> e. The areal density of the bypass caps used.
>>> =20
>>> b/c/d Determine the mounted inductance of each cap. X2Y(r)'s=20
>>> and IDC(r)'s yield the best results. In all cases the via=20
>>> pattern used makes a big difference in the number of caps=20
>>> used and the behavior at parallel resonance. In my mind it=20
>>> is a lot better to floor plan bypass caps w/ optimal via=20
>>> patterns up front, than to have the PCB designer try to fit=20
>>> them in later.
>>> =20
>>> 3) As the power cavity is made thinner, six notable things happen:
>>> =20
>>> a. The horizontal spreading inductance of the planes falls. =20
>>> The extremes for six layer 0.062" stack-ups can be almost=20
>>> 10:1 going from a
>>> 4 mil to a 38 mil power core.
>>> b. The high frequency impedance of the power system comes=20
>>> down. On the bad side one will be in PCB wave effects at=20
>>> lower frequencies. Detuning w/ discretes takes about the=20
>>> same number of parts independent of the cavity thickness. =20
>>> Tolerances are more forgiving for the thinner cavity.
>>> c. The parallel resonant frequency of the power system comes=20
>>> down as the square root of the power cavity thickness. =20
>>> Typical resonant frequencies typically vary over a 300MHz to=20
>>> 1.5GHz range depending on bypass scheme over the 4mil to=20
>>> 38mil cavity thicknesses.
>>> d. The Q of the parallel resonance goes up. On the good=20
>>> side, higher Qs=20
>>> are generally easier to detune. The bad side is that the natural=20
>>> magnitude of Zpeak is fairly independent of the cavity=20
>>> thickness, now it is much more likely to be where there is=20
>>> more signal energy. The moral here is: detune the resonance.
>>> e. Above and below the resonant frequency noise attenuation improves.
>>> f. The asymmetry between outer and inner routing layers in a=20
>>> 6 layer stack-up become more pronounced and routing density=20
>>> can suffer severely. Maintaining 50Ohms and/or acceptable=20
>>> cross talk values on outer layers more than about 10 mils=20
>>> from an image plane demands some rather wide traces and=20
>>> routing pitches.
>>> =20
>>> 4) An S1 G S2 S3 P S4 stack-up works best when the highest=20
>>> speed signals can be broken out and routed completely on S1. =20
>>> Otherwise S1 P S2 S3 G
>>> S4 is usually better breaking out high speed signals on layer=20
>>> S4 first and layer S3 second, minimizing via stubs. In=20
>>> either case prioritizing the traces with the most high speed=20
>>> energy to the routing layer(s) adjacent an image plane=20
>>> connected to the dominant coupling rail in the IC will help=20
>>> reduce demands on the PDN. That rail is usually ground.
>>> =20
>>> Best Regards,
>>> =20
>>> Steve.
>>> =20
>>> =20
>>> DAVID CUTHBERT wrote:
>>>
>>>> Fernando,
>>>> The S1 S2 G P S3 S4 stackup can provide excellent power plane=20
>>>> performance at the expense of S1 and S4. Routing S1 and S4=20
>>>>
>>> mostly at=20
>>>
>>>> right angles to S2 and
>>>> S3 can greatly reduce the crosstalk. And using narrow traces to=20
>>>> maintain the Z0 of S1 and S4 will take care of the Z0.
>>>>
>>>> I often use S1 G S2 - S3 P S4 for 6-layer boards. The=20
>>>>
>>> signal traces=20
>>>
>>>> are nicely isolated with a 62 mil board having spacing like so:
>>>> 10 mils, 5 mils, 22 mils, 5 mils, 10 mils. The tradeoff is that the=20
>>>> power plane Z0 is about 2X that of a board having 10 mils=20
>>>>
>>> between each=20
>>>
>>>> layer. The power plane Z0 is still quite low with an inductance of=20
>>>> about 200 pH per square. Contrast this to an S1-G via inductance of=20
>>>> about 300 pH and the plane Z does not dominate things.
>>>>
>>>> Dave Cuthbert
>>>> NARTE Certified EMC Engineer
>>>> Consulting, SI, EMC, power electronics, analog of all kinds
>>>>
>>>>
>>>> On Wed, Feb 20, 2008 at 2:17 PM, Fernando Yuitiro Mori=20
>>>> <mori@xxxxxxxxxxxxx>
>>>> wrote:
>>>>
>>>> =20
>>>>
>>>>> Hi,
>>>>> I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I=20
>>>>>
>>> need the 4=20
>>>
>>>>> layer with 60 ohms, so there are some problem if I use S1=20
>>>>>
>>> G S2 S3 P S4?
>>>
>>>>> Regards,
>>>>>
>>>>> Fernando Mori
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>>> --
>>> Steve Weir
>>> Teraspeed Consulting Group LLC
>>> 121 North River Drive
>>> Narragansett, RI 02882=20
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>>> (408) 884-3985 Business
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>>
>
--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(408) 884-3985 Business
(707) 780-1951 Fax
Main office
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