[SI-LIST] Re: 6 layers stackup

Scott, Lee's metric is for a single via.  He divides that by the total 
number of vias.  So for example, an 0402 with two vias he would factor 
at 35pH / 2 or 17.5pH / mil.  It's a little low versus the theoretical 
value of 21pH / mil for 10mil drills on 1mm pitch, but is in the ballpark.

Best Regards,


Steve.

Scott McMorrow wrote:
> Lee,
>
> That depends on your via size, spacing and where the planes are 
> located w.r.t. the capacitor.  The via pair inductance is:
>
> Lmounting vias - 5.08 pH/mil x 2 x H x ln(2S/D)
>
> as reported by Howard Johnson from a closed form solution.
>
> where
>
> H is the length of the vias in the plane cavities
> S is the center to center via separation
> D is the via diameter
>
> If we use 10 mil vias at a 30 mil spacing, then our inductance is
>
> 18.2 pH/mil
>
> If we use 15 mil vias at 40 mil spacing, our inductance is:
>
> 17pH/mil
>
> To get your number of 35 pH/mil, we would need to use 10 mil vias and 
> space them approximately 150 mils apart.  So, to start with, your 
> approximate via inductance is high by a factor of 2 to 1.
>
> 15 to 20 pH is a much better number for vias on well-mounted 
> capacitors.  So, if we place the planes at 3 mil and 7 mil below the 
> surface of the board where the capacitors are mounted, the via 
> inductance is 140 pH.  Certainly this is less than the inductance of 
> an 0402 capacitor, which is approximately 450 pH.  A so-called "magic 
> capacitor", with an inductance of 120 pH would most necessarily 
> provide a significant reduction in total mounted inductance.  Last I 
> checked
> 120 + 140 is much less than 450 + 140.   In addition, those "magic 
> capacitors" take advantage of mutual inductance coupling between the 
> vias, while using more vias, by a factor of about 4:1 (5 pH/mil vs. 20 
> pH/mil). In which case the inductance for the "magic capacitor" 
> solution is:
>
> 120 pH + 35 pH = 155 pH
>
> Last time I measured this and simulated this
>
> 155 pH is << than 590 pH, or about 3.8:1 difference.
>
> Since the ratio of vias used for an X2Y capacitor vs an 0402 is 6:2 or 
> 3:1.  The via inductance efficiency ratio is;
>
> 1.27:1
>
> That is, an X2Y capacitor is at least 1.27 times more efficient in 
> using vias than an 0402 capacitor.
>
> This has been confirmed multiple times by measurements and by 
> electromagnetic simulation.
>
> Now, I do agree that the further down you reach into the cavity, the 
> less benefit that you get.  However, the via efficiency ratio of 
> "magic capacitors" continue to be significantly better than 
> conventional MLCC capacitors, no matter where the planes are placed in 
> the stack.
>
>
> regards,
>
> Scott
>
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
> Teraspeed® is the registered service mark of
> Teraspeed Consulting Group LLC
>   
>
>
> Lee Ritchey wrote:
>> I disagree that ultralow inductance capacitors perform significantly better
>> that standard two leaded capacitors such as 0402 and 0603 due to the added
>> inductance associated with the mounting pads and mounting vias.  This has
>> been supported many times by physical measurements on real PCBs and is
>> documented in my book, "Right the First Time, A Practical Handbook on High
>> Speed PCB and Systetm Design" as well as in several other sources.
>>
>> I am mystified at how it can be claimed that this is not so when the
>> inductance of the vias connecting capacitors to the associated planes
>> averages something like 35 pH per mil of length- no matter what  kind of
>> magical capacitor they are connected to.  It is especially true when one is
>> speaking of a six layer PCB that has planes 20-40 mils below the surface. 
>> That is 0.7 nH to 1.4 nH per lead.  Even if the capacitor has 0.1 nH
>> inductance as an IDC capacitor is said to have, the total inductance is
>> driven up near 1 nH.  How can any capacitor make this go away?
>>
>> It is time to stop pretending that there are magic capacitors out there.
>>
>> Lee Ritchey
>> Speeding Edge.
>>
>>
>>   
>>> [Original Message]
>>> From: steve weir <weirsi@xxxxxxxxxx>
>>> To: QU Perry <Perry.Qu@xxxxxxxxxxxxxxxxxx>
>>> Cc: <si-list@xxxxxxxxxxxxx>
>>> Date: 2/25/2008 11:52:30 AM
>>> Subject: [SI-LIST] Re: 6 layers stackup
>>>
>>> Perry, the discussion has been limited to 4/6 layer boards with a single 
>>> symmetric power cavity.  The Z axis inductance for an IC or bypass cap 
>>> to the cavity depends on the distance to the center of the cavity.  With 
>>> a single, symmetric cavity, that is going to be half the board 
>>> thickness.  This is not to be confused with higher layer count boards 
>>> where we can place at least one modestly thin cavity near the IC / 
>>> capacitor mounting surface.  In all cases, the cavity spreading 
>>> inductance becomes a limiting factor in PDN impedance.  Cavity impedance 
>>> varies directly with cavity height.
>>>
>>> In the case of any almost thickness PCB, the via attachment structure is 
>>> a significant, if not dominant contributor to the mounted capacitor 
>>> inductance, that is the inductance as seen at that attachment point at 
>>> the planes.  Capacitors like X2Y(r)'s, and IDC(r)'s when properly 
>>> attached yield much lower inductance than discrete caps.  This is 
>>> readily modeled in any number of tools, and confirmed by properly 
>>> constructed experiments.  So low inductance caps still work, whether or 
>>> not you have a thin cavity, and whether or not the cavity is adjacent to 
>>> the caps.
>>>
>>> We are talking about two different resonances.  The resonance that you 
>>> are referring to are the half-wave modes.  I am talking about the 
>>> parallel resonance between the bypass network and the power cavity.  
>>> This is the beast that eats most people's lunch.  It is a matter of 
>>> capacitance per unit area of the cavity which depends directly on 
>>> height, and the area / unit inductance of the bypass network.
>>>
>>> Best Regards,
>>>
>>>
>>> Steve.
>>>
>>> QU Perry wrote:
>>>     
>>>> Steve:
>>>>
>>>> My understanding on the impact of thinner power cavity is mainly the
>>>> reduction of spread inductance, such that any added benefit of IDC/X2Y
>>>> placed at the peripheral of BGA will not be compromised by the planes..
>>>> In most applications however, we rely heavily on the decoupling caps
>>>> (0402) directly placed underneath BGAs, and in those cases, I would
>>>> think thickness of power cavity is not important as the total inductance
>>>> looking into PCB from BGA pads to the planes and to the decoupling caps
>>>> don't change. Your thoughts ?
>>>>
>>>> I'm also not clear when you say parallel resonance frequency is driven
>>>> by thickness. Comparing Z dimension vs. X/Y for a normal power plane/PCB
>>>> thickness, I would say the resonance frequency is mainly determined by
>>>> how big the plane is not how thick the cavity ?
>>>>
>>>> Thanks
>>>>
>>>> Perry
>>>>
>>>> ======================================= 
>>>>
>>>> Perry Qu 
>>>>
>>>> Design & Qualification, Alcatel-Lucent Canada Inc.
>>>>
>>>> 600 March Road, Ottawa ON, K2K 2E6, Canada 
>>>>
>>>> DID: 613-7846720  Fax: 613-5993642 
>>>>
>>>> Email: perry.qu@xxxxxxxxxxxxxxxxxx 
>>>>
>>>> ======================================= 
>>>>
>>>>  
>>>>
>>>>   
>>>>       
>>>>> -----Original Message-----
>>>>> From: si-list-bounce@xxxxxxxxxxxxx 
>>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
>>>>> Sent: Saturday, February 23, 2008 6:44 PM
>>>>> To: DAVID CUTHBERT
>>>>> Cc: Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
>>>>> Subject: [SI-LIST] Re: 6 layers stackup
>>>>>
>>>>> Dave, Fernando my $0.02 on 4/6 layer stack-ups with a single 
>>>>> symmetric power cavity:
>>>>>
>>>>> 1) The Z-axis inductance seen at the IC solder pads to the 
>>>>> power cavity is pretty much fixed by:
>>>>>
>>>>> a. The total thickness of the PCB.
>>>>> b. The pin-out of the IC.
>>>>> c. The via drill diameter.
>>>>>
>>>>> 2) Similarly the Z-axis inductance seen between the bypass 
>>>>> caps and the power cavity is fixed by:
>>>>>
>>>>> a. The total thickness of the PCB.
>>>>> b. The type of bypass capacitors used.
>>>>> c. The via pattern used w/ the bypass caps.
>>>>> d. The via drill diameter.
>>>>> e. The areal density of the bypass caps used.
>>>>>
>>>>> b/c/d Determine the mounted inductance of each cap.  X2Y(r)'s 
>>>>> and IDC(r)'s yield the best results.  In all cases the via 
>>>>> pattern used makes a big difference in the number of caps 
>>>>> used and the behavior at parallel resonance.  In my mind it 
>>>>> is a lot better to floor plan bypass caps w/ optimal via 
>>>>> patterns up front, than to have the PCB designer try to fit 
>>>>> them in later.
>>>>>
>>>>> 3) As the power cavity is made thinner, six notable things happen:
>>>>>
>>>>> a. The horizontal spreading inductance of the planes falls.  
>>>>> The extremes for six layer 0.062" stack-ups can be almost 
>>>>> 10:1 going from a
>>>>> 4 mil to a 38 mil power core.
>>>>> b. The high frequency impedance of the power system comes 
>>>>> down.  On the bad side one will be in PCB wave effects at 
>>>>> lower frequencies.  Detuning w/ discretes takes about the 
>>>>> same number of parts independent of the cavity thickness.  
>>>>> Tolerances are more forgiving for the thinner cavity.
>>>>> c. The parallel resonant frequency of the power system comes 
>>>>> down as the square root of the power cavity thickness.  
>>>>> Typical resonant frequencies typically vary over a 300MHz to 
>>>>> 1.5GHz range depending on bypass scheme over the 4mil to 
>>>>> 38mil cavity thicknesses.
>>>>> d. The Q of the parallel resonance goes up.  On the good 
>>>>> side, higher Qs 
>>>>> are generally easier to detune.   The bad side is that the natural 
>>>>> magnitude of Zpeak is fairly independent of the cavity 
>>>>> thickness, now it is much more likely to be where there is 
>>>>> more signal energy.  The moral here is:  detune the resonance.
>>>>> e. Above and below the resonant frequency noise attenuation improves..
>>>>> f. The asymmetry between outer and inner routing layers in a 
>>>>> 6 layer stack-up become more pronounced and routing density 
>>>>> can suffer severely.  Maintaining 50Ohms and/or acceptable 
>>>>> cross talk values on outer layers more than about 10 mils 
>>>>> from an image plane demands some rather wide traces and 
>>>>> routing pitches.
>>>>>
>>>>> 4) An S1 G S2 S3 P S4 stack-up works best when the highest 
>>>>> speed signals can be broken out and routed completely on S1.  
>>>>> Otherwise S1 P S2 S3 G
>>>>> S4 is usually better breaking out high speed signals on layer 
>>>>> S4 first and layer S3 second, minimizing via stubs.  In 
>>>>> either case prioritizing the traces with the most high speed 
>>>>> energy to the routing layer(s) adjacent an image plane 
>>>>> connected to the dominant coupling rail in the IC will help 
>>>>> reduce demands on the PDN.  That rail is usually ground.
>>>>>
>>>>> Best Regards,
>>>>>
>>>>> Steve.
>>>>>
>>>>>
>>>>> DAVID CUTHBERT wrote:
>>>>>     
>>>>>         
>>>>>> Fernando,
>>>>>> The S1 S2 G P S3 S4 stackup can provide excellent power plane 
>>>>>> performance at the expense of S1 and S4. Routing S1 and S4 
>>>>>>       
>>>>>>           
>>>>> mostly at 
>>>>>     
>>>>>         
>>>>>> right angles to S2 and
>>>>>> S3 can greatly reduce the crosstalk. And using narrow traces to 
>>>>>> maintain the Z0 of S1 and S4 will take care of the Z0.
>>>>>>
>>>>>> I often use S1 G S2 -  S3 P S4 for 6-layer boards. The 
>>>>>>       
>>>>>>           
>>>>> signal traces 
>>>>>     
>>>>>         
>>>>>> are nicely isolated with a 62 mil board having spacing like so:
>>>>>> 10 mils, 5 mils, 22 mils, 5 mils, 10 mils. The tradeoff is that the 
>>>>>> power plane Z0 is about 2X that of a board having 10 mils 
>>>>>>       
>>>>>>           
>>>>> between each 
>>>>>     
>>>>>         
>>>>>> layer. The power plane Z0 is still quite low with an inductance of 
>>>>>> about 200 pH per square. Contrast this to an S1-G via inductance of 
>>>>>> about 300 pH and the plane Z does not dominate things.
>>>>>>
>>>>>>      Dave Cuthbert
>>>>>>      NARTE Certified EMC Engineer
>>>>>>      Consulting, SI, EMC, power electronics, analog of all kinds
>>>>>>
>>>>>>
>>>>>> On Wed, Feb 20, 2008 at 2:17 PM, Fernando Yuitiro Mori 
>>>>>> <mori@xxxxxxxxxxxxx>
>>>>>> wrote:
>>>>>>
>>>>>>   
>>>>>>       
>>>>>>           
>>>>>>> Hi,
>>>>>>> I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I 
>>>>>>>         
>>>>>>>             
>>>>> need the 4 
>>>>>     
>>>>>         
>>>>>>> layer with 60 ohms, so there are some problem if I use S1 
>>>>>>>         
>>>>>>>             
>>>>> G S2 S3 P S4?
>>>>>     
>>>>>         
>>>>>>> Regards,
>>>>>>>
>>>>>>> Fernando Mori
>>>>>>> ------------------------------------------------------------------
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>>>>>>
>>>>>>   
>>>>>>       
>>>>>>           
>>>>> --
>>>>> Steve Weir
>>>>> Teraspeed Consulting Group LLC
>>>>> 121 North River Drive
>>>>> Narragansett, RI 02882 
>>>>>
>>>>> California office
>>>>> (408) 884-3985 Business
>>>>> (707) 780-1951 Fax
>>>>>
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>>>>> This e-mail contains proprietary and confidential 
>>>>> intellectual property of Teraspeed Consulting Group LLC
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>>>>>     
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>>>>   
>>>>       
>>> -- 
>>> Steve Weir
>>> Teraspeed Consulting Group LLC 
>>> 121 North River Drive 
>>> Narragansett, RI 02882 
>>>
>>> California office
>>> (408) 884-3985 Business
>>> (707) 780-1951 Fax
>>>
>>> Main office
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>>> This e-mail contains proprietary and confidential intellectual property
>>>     
>> of Teraspeed Consulting Group LLC
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-- 
Steve Weir
Teraspeed Consulting Group LLC 
121 North River Drive 
Narragansett, RI 02882 

California office
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(707) 780-1951 Fax

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