[SI-LIST] Re: 6 layers stackup

This is a common misconception - your calculator may give the same trace
impedance whether it is over power or ground, but the emission potential
is much higher over power than ground. 
 

I tell my group to think of the VCC planes as "carrier signals" and the
noise as modulation. 

 

The good news is that noise on VCC can be filtered easily while that on
ground is much harder.

 

I think we all agree there are trade-offs between the stack-ups and we
go through these weekly with customers. There is no one right answer. 

 

 
Curt

 

 

Curt McNamara, P.E. // principal electrical engineer 
Logic Product Development
411 Washington Ave. N. Suite 400
Minneapolis, MN 55401
T // 612.436.5178
F // 612.672.9489
www.logicpd.com <http://www.logicpd.com/>  
/ / / / / / / / / / / / / / / / / / / / / / / / / 
This message (including any attachments) contains confidential
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From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx] 
Sent: Monday, February 25, 2008 12:16 PM
To: Curt McNamara
Cc: steve weir; DAVID CUTHBERT; Fernando Yuitiro Mori;
si-list@xxxxxxxxxxxxx
Subject: Re: [!! SPAM] [SI-LIST] Re: 6 layers stackup

 

Curt

Actually, to be technically correct, the impedance of the top layer
traces are the same whether a ground or a power layer is used directly
under the surface. It is the transition from package to PCB that can
cause common modes to occur, with subsequent radiation.  Whether or not
that happens is dependent, not upon what layer is used underneath the
traces, but rather, what the signals were referenced to prior to exit
from the package body, and the loop area between the signal balls/pins
and reference balls/pins.

Many packages use ground referenced traces, therefore ground referencing
of the traces on the top layer of a PCB will lower common mode crosstalk
and subsequent emissions.  However, not all packages utilize ground
referencing for all signals.  Nor do all packages keep the loop area
between the signal and return path through the balls/pins small.  In
those cases, there will be ample common mode noise traveling across the
nearest plane.


regards,

Scott



Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
 
http://www.teraspeed.com
 
Teraspeed(r) is the registered service mark of
Teraspeed Consulting Group LLC



Curt McNamara wrote: 

Steve, every trace on the surface and the IC packages are exposed =
antennas! Ground under the surface allows lower impedance of traces and
=
crystals along with lower package impedance to GND (lower Vss bounce in
=
your terms).=20
 
To translate your other point: having traces inside the power<> ground =
pair traps that energy, which can excite the planes and the cavity. This
=
is another part of the trade-off. So if we have to use S1 G S2 S3 P S4 =
we route critical traces on the surface layers.
 
                                                             Curt
 
 
Curt McNamara, P.E.=A0// principal electrical engineer=20
Logic Product Development
411 Washington Ave. N. Suite 400
Minneapolis, MN 55401
T // 612.436.5178
F // 612.672.9489
www.logicpd.com=20
/ / / / / / / / / / / / / / / / / / / / / / / / /=20
This message (including any attachments) contains confidential =
information intended for a specific individual and purpose, and is =
protected by law. If you are not the intended recipient, you should =
delete this message and are hereby notified that any disclosure, =
copying, or distribution of this message, or the taking of any action =
based on it, is strictly prohibited.
 
 
 
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
Sent: Monday, February 25, 2008 11:19 AM
To: Curt McNamara
Cc: DAVID CUTHBERT; Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: 6 layers stackup
 
Curt, from the emissions stand-point, Vss bounce matters when that=20
bounce occurs on an exposed antenna.  Sometimes a die w/o a heatsink=20
above the planes forms that antenna and reducing the loop height to
Vss=20
is helpful.  In one of life's nothing comes for free categories is
the=20
problem that for CMOS the greater the I/O coupling through the PDN
is:=20
the greater the tendency for both the I/O signals and the PDN to both=20
radiate, and the greater I/O susceptibility to external disturbances.
 
Best Regards,
 
 
Steve.
 
Curt McNamara wrote:
  

        Steve, that is true for the designs we do as well. The trade-off
seems =
            

to be trace impedance. With traces inside the power<>ground pair then =
impedance matching between layers is closer, but at the cost of =
inter-plane capacitance and all its benefits.
  

        Since a main concern of ours is emissions and immunity,
reduction of =
            

common mode (your Vss bounce) is more important than Vcc bounce, which =
can be dealt with other ways.
  

                                                               Curt
         
         
        Curt McNamara, P.E. // principal electrical engineer=20
        Logic Product Development
        411 Washington Ave. N. Suite 400
        Minneapolis, MN 55401
        T // 612.436.5178
        F // 612.672.9489
        www.logicpd.com=20
        / / / / / / / / / / / / / / / / / / / / / / / / /=20
        This message (including any attachments) contains confidential =
            

information intended for a specific individual and purpose, and is =
protected by law. If you are not the intended recipient, you should =
delete this message and are hereby notified that any disclosure, =
copying, or distribution of this message, or the taking of any action =
based on it, is strictly prohibited.
  

         
        -----Original Message-----
        From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
        Sent: Monday, February 25, 2008 10:46 AM
        To: Curt McNamara
        Cc: DAVID CUTHBERT; Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
        Subject: Re: [SI-LIST] Re: 6 layers stackup
         
        Curt, true Vss bounce improves when Vss is closest to the IC,
just the =
            

 
  

        same as Vcc bounce improves when it is closest.  But for most
4/6 =
            

layer=20
  

        PCB circumstances I find I lose more by making Vss the near
plane than =
            

I=20
  

        gain.
         
        Best Regards,
         
         
        Steve.
        Curt McNamara wrote:
         =20
            

                One other point about stack-ups -- putting ground near
the top layer =
                      

provides lower impedance to ground for any IC packages located there.
  

                 
                                                                 Curt
                 
                 
                Curt McNamara, P.E. // principal electrical engineer=20
                Logic Product Development
                411 Washington Ave. N. Suite 400
                Minneapolis, MN 55401
                T // 612.436.5178
                F // 612.672.9489
                www.logicpd.com=20
                / / / / / / / / / / / / / / / / / / / / / / / / /=20
                This message (including any attachments) contains
confidential =
                      

information intended for a specific individual and purpose, and is =
protected by law. If you are not the intended recipient, you should =
delete this message and are hereby notified that any disclosure, =
copying, or distribution of this message, or the taking of any action =
based on it, is strictly prohibited.
  

                 
                 
                -----Original Message-----
                From: si-list-bounce@xxxxxxxxxxxxx =
                      

[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
  

                Sent: Saturday, February 23, 2008 5:44 PM
                To: DAVID CUTHBERT
                Cc: Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
                Subject: [SI-LIST] Re: 6 layers stackup
                 
                Dave, Fernando my $0.02 on 4/6 layer stack-ups with a
single =
                      

symmetric=20
  

                power cavity:
                 
                1) The Z-axis inductance seen at the IC solder pads to
the power =
                      

cavity=20
  

                is pretty much fixed by:
                 
                a. The total thickness of the PCB.
                b. The pin-out of the IC.
                c. The via drill diameter.
                 
                2) Similarly the Z-axis inductance seen between the
bypass caps and =
                      

the=20
  

                power cavity is fixed by:
                 
                a. The total thickness of the PCB.
                b. The type of bypass capacitors used.
                c. The via pattern used w/ the bypass caps.
                d. The via drill diameter.
                e. The areal density of the bypass caps used.
                 
                b/c/d Determine the mounted inductance of each cap.
X2Y(r)'s and=20
                IDC(r)'s yield the best results.  In all cases the via
pattern used=20
                makes a big difference in the number of caps used and
the behavior at =
                      

 
  

                parallel resonance.  In my mind it is a lot better to
floor plan =
                      

bypass=20
  

                caps w/ optimal via patterns up front, than to have the
PCB designer =
                      

try=20
  

                to fit them in later.
                 
                3) As the power cavity is made thinner, six notable
things happen:
                 
                a. The horizontal spreading inductance of the planes
falls.  The=20
                extremes for six layer 0.062" stack-ups can be almost
10:1 going from =
                      

a=20
  

                4 mil to a 38 mil power core.
                b. The high frequency impedance of the power system
comes down.  On =
                      

the=20
  

                bad side one will be in PCB wave effects at lower
frequencies.  =
                      

Detuning=20
  

                w/ discretes takes about the same number of parts
independent of the=20
                cavity thickness.  Tolerances are more forgiving for the
thinner =
                      

cavity.
  

                c. The parallel resonant frequency of the power system
comes down as =
                      

the=20
  

                square root of the power cavity thickness.  Typical
resonant =
                      

frequencies=20
  

                typically vary over a 300MHz to 1.5GHz range depending
on bypass =
                      

scheme=20
  

                over the 4mil to 38mil cavity thicknesses.
                d. The Q of the parallel resonance goes up.  On the good
side, higher =
                      

Qs=20
  

                are generally easier to detune.   The bad side is that
the natural=20
                magnitude of Zpeak is fairly independent of the cavity
thickness, now =
                      

it=20
  

                is much more likely to be where there is more signal
energy.  The =
                      

moral=20
  

                here is:  detune the resonance.
                e. Above and below the resonant frequency noise
attenuation improves.
                f. The asymmetry between outer and inner routing layers
in a 6 layer=20
                stack-up become more pronounced and routing density can
suffer=20
                severely.  Maintaining 50Ohms and/or acceptable cross
talk values on=20
                outer layers more than about 10 mils from an image plane
demands some =
                      

 
  

                rather wide traces and routing pitches.
                 
                4) An S1 G S2 S3 P S4 stack-up works best when the
highest speed =
                      

signals=20
  

                can be broken out and routed completely on S1.
Otherwise S1 P S2 S3 =
                      

G=20
  

                S4 is usually better breaking out high speed signals on
layer S4 =
                      

first=20
  

                and layer S3 second, minimizing via stubs.  In either
case =
                      

prioritizing=20
  

                the traces with the most high speed energy to the
routing layer(s)=20
                adjacent an image plane connected to the dominant
coupling rail in =
                      

the=20
  

                IC will help reduce demands on the PDN.  That rail is
usually ground.
                 
                Best Regards,
                 
                Steve.
                 
                 
                DAVID CUTHBERT wrote:
                 =20
                   =20
                      

                        Fernando,
                        The S1 S2 G P S3 S4 stackup can provide
excellent power plane =
                                

performance at
  

                        the expense of S1 and S4. Routing S1 and S4
mostly at right angles =
                                

to S2 and
  

                        S3 can greatly reduce the crosstalk. And using
narrow traces to =
                                

maintain the
  

                        Z0 of S1 and S4 will take care of the Z0.
                         
                        I often use S1 G S2 -  S3 P S4 for 6-layer
boards. The signal traces =
                                

are
  

                        nicely isolated with a 62 mil board having
spacing like so:
                        10 mils, 5 mils, 22 mils, 5 mils, 10 mils. The
tradeoff is that the =
                                

power
  

                        plane Z0 is about 2X that of a board having 10
mils between each =
                                

layer. The
  

                        power plane Z0 is still quite low with an
inductance of about 200 pH =
                                

per
  

                        square. Contrast this to an S1-G via inductance
of about 300 pH and =
                                

the
  

                        plane Z does not dominate things.
                         
                             Dave Cuthbert
                             NARTE Certified EMC Engineer
                             Consulting, SI, EMC, power electronics,
analog of all kinds
                         
                         
                        On Wed, Feb 20, 2008 at 2:17 PM, Fernando
Yuitiro Mori =
                                

<mori@xxxxxxxxxxxxx> <mailto:mori@xxxxxxxxxxxxx> 
  

                        wrote:
                         
                         =20
                           =20
                             =20
                                

                                Hi,
                                I normally use S1 S2 G P S3 S4 for the 6
layers stackup. I need the =
                                          

4
  

                                layer with 60 ohms, so there are some
problem if I use S1 G S2 S3 P =
                                          

S4?
  

                                Regards,
                                 
                                Fernando Mori
        
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--=20
Steve Weir
Teraspeed Consulting Group LLC=20
121 North River Drive=20
Narragansett, RI 02882=20
 
California office
(408) 884-3985 Business
(707) 780-1951 Fax
 
Main office
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