Posts for si-list, 02-2008

Browse: Last Month: 01-2008 Main Archive Page Next Month: 03-2008

» [SI-LIST] Partnering opportunities for experienced waveform integrity engineers -
» [SI-LIST] Re: Improving Power Delivery Performance Seminar, March 19, 1:00pm~4:00pm, San Jose DoubleTree Hotel -
» [SI-LIST] Re: Improving Power Delivery Performance Seminar, March 19, 1:00pm~4:00pm, San Jose DoubleTree Hotel -
» [SI-LIST] Re: Improving Power Delivery Performance Seminar, March 19, 1:00pm~4:00pm, San Jose DoubleTree Hotel -
» [SI-LIST] Summer intern -
» [SI-LIST] Re: HOW to use IBIS in HSPICE -
» [SI-LIST] Improving Power Delivery Performance Seminar, March 19, 1:00pm~4:00pm, San Jose DoubleTree Hotel -
» [SI-LIST] HOW to use IBIS in HSPICE -
» [SI-LIST] Re: [SI-LIST]6 layers stackup -
» [SI-LIST] Re: [SI-LIST]6 layers stackup -
» [SI-LIST] Re: Is there any relationship between IBIS simulation accuracy and frequency? -
» [SI-LIST] Re: Interplane capacitance efective frequency range -
» [SI-LIST] Re: [SI-LIST]6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: [SI-LIST]6 layers stackup - proof -
» [SI-LIST] Re: [SI-LIST]6 layers stackup -
» [SI-LIST] Re: Interplane capacitance efective frequency range -
» [SI-LIST] Re: [SI-LIST]6 layers stackup - proof -
» [SI-LIST] Re: [SI-LIST]6 layers stackup - proof -
» [SI-LIST] Interplane capacitance efective frequency range -
» [SI-LIST] Re: [SI-LIST]6 layers stackup - proof -
» [SI-LIST] Re: [SI-LIST]6 layers stackup - proof -
» [SI-LIST] Re: [SI-LIST]6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: high ESR caps -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: high ESR caps -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] high ESR caps -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: Is there any relationship between IBIS simulation accuracy and frequency? -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] SI Job Opening at Spansion -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: Is there any relationship between IBIS simulation accuracy and frequency? -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: Differential Signals with changed ground references -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: ICX / Connector IBIS files -
» [SI-LIST] ICX / Connector IBIS files -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Differential Signals with changed ground references -
» [SI-LIST] R: Is there any relationship between IBIS simulation accuracy and frequency? -
» [SI-LIST] Re: Is there any relationship between IBIS simulation accuracy and frequency? -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Is there any relationship between IBIS simulation accuracy and frequency? -
» [SI-LIST] Solder made obsolete by growing copper pillars -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] SI Engineer openning at Marvell Shanghai -
» [SI-LIST] Re: connector design question -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] connector design question -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup -
» [SI-LIST] Re: Difference between FR-408 (Isola)and NP 4000-13EP -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: Difference between FR-408 (Isola)and NP 4000-13EP -
» [SI-LIST] Re: Difference between FR-408 (Isola)and NP 4000-13EP -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Difference between FR-408 (Isola)and NP 4000-13EP -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: inter-cabinet connections -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: test, please ignore -
» [SI-LIST] Re: test, please ignore -
» [SI-LIST] Re: test, please ignore -
» [SI-LIST] Re: test, please ignore -
» [SI-LIST] test, please ignore -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: using IBIS FILE which point is simulated? -
» [SI-LIST] Re: using IBIS FILE which point is simulated? -
» [SI-LIST] Re: using IBIS FILE which point is simulated? -
» [SI-LIST] using IBIS FILE which point is simulated? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: How to do analysis for Clock signals -
» [SI-LIST] Re: How to do analysis for Clock signals -
» [SI-LIST] FW: Signal Integrity Opportunity - San Jose, CA -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: inter-cabinet connections -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: Hyperlynx modelling of 'wire over ground' -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] How to do analysis for Clock signals -
» [SI-LIST] inter-cabinet connections -
» [SI-LIST] Open Rec at Xilinx -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: 6 layers stackup -
» [SI-LIST] Re: Hyperlynx modelling of 'wire over ground' -
» [SI-LIST] 6 layers stackup -
» [SI-LIST] Re: Hyperlynx modelling of 'wire over ground' -
» [SI-LIST] Re: Hyperlynx modelling of 'wire over ground' -
» [SI-LIST] Re: Hyperlynx modelling of 'wire over ground' -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: SI and CAD engineer job opportunities at Cisco in Shanghai, China -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] Re: transformers -
» [SI-LIST] Re: TDR vs. VNA? Which to purchase? -
» [SI-LIST] TDR vs. VNA? Which to purchase? -
» [SI-LIST] Hyperlynx modelling of 'wire over ground' -
» [SI-LIST] SI and CAD engineer job opportunities at Cisco in Shanghai, China -
» [SI-LIST] Re: Capacitance of TVS in FE/GE application -
» [SI-LIST] Capacitance of TVS in FE/GE application -
» [SI-LIST] Re: transformers -
» [SI-LIST] Re: transformers -
» [SI-LIST] transformers -
» [SI-LIST] Re: Skin Effect on Power/ground Plane -
» [SI-LIST] Power Plane Impedance -
» [SI-LIST] Re: Skin Effect on Power/ground Plane -
» [SI-LIST] Re: Skin Effect on Power/ground Plane -
» [SI-LIST] Re: Skin Effect on Power/ground Plane -
» [SI-LIST] Re: Cumulative Jitter Analysis -
» [SI-LIST] Re: SGMII ROUTING LENGTH RESTRICTION -
» [SI-LIST] Re: Cumulative Jitter Analysis -
» [SI-LIST] Cumulative Jitter Analysis -
» [SI-LIST] Re: Skin Effect on Power/ground Plane -
» [SI-LIST] SGMII ROUTING LENGTH RESTRICTION -
» [SI-LIST] Re: Skin Effect on Power/ground Plane -
» [SI-LIST] Skin Effect on Power/ground Plane -
» [SI-LIST] Re: mSPICE -
» [SI-LIST] mSPICE -
» [SI-LIST] European IBIS Summit at DATe 2008 - Second Call for Call for Paticipation -
» [SI-LIST] Etiquette and other good intentions -
» [SI-LIST] Re: Test of new reply-to address -
» [SI-LIST] Re: Long Term storage of partially assembled Board or Assembly Storage to 25 years: Concerns are about connector and PCB quality after this time. -
» [SI-LIST] Re: Long Term storage of partially assembled Board or Assembly Storage to 25 years: Concerns are about connector and PCB quality after this time. -
» [SI-LIST] Long Term storage of partially assembled Board or Assembly Storage to 25 years: Concerns are about connector and PCB quality after this time. -
» [SI-LIST] Test of new reply-to address -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Test -
» [SI-LIST] Re: Random behaiour of Virtex 4 FPGA -
» [SI-LIST] Re: Random behaiour of Virtex 4 FPGA -
» [SI-LIST] Re: Random behaiour of Virtex 4 FPGA -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Re: Random behaiour of Virtex 4 FPGA -
» [SI-LIST] Random behaiour of Virtex 4 FPGA -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] IBIS model for PCI copper fingers of the PCI extension card -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Re: file conversion -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] two DesignCon 2008 SI papers posted on BeTheSignal.com -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Re: What is meant by a differential signal -
» [SI-LIST] Re: file conversion -
» [SI-LIST] Re: file conversion -
» [SI-LIST] Re: file conversion -
» [SI-LIST] Re: file conversion -
» [SI-LIST] Re: file conversion -
» [SI-LIST] file conversion -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Re: list etiquette -
» [SI-LIST] Re: list etiquette -
» [SI-LIST] Re: list etiquette -
» [SI-LIST] Re: list etiquett -
» [SI-LIST] Presentations available from the IBIS Summit at DesignCon 2008! -
» [SI-LIST] list etiquett -
» [SI-LIST] Using Resonance to measure circit parameters - BNC barrel example -
» [SI-LIST] DDR strobe to clock length matching -
» [SI-LIST] IEEE-EMC Society-- Santa Clara Valley Chapter, February 2008 meeting. [Presenter: Steve Weir] -
» [SI-LIST] high current shorting link -
» [SI-LIST] Antw: Re: EPD Guidelines -
» [SI-LIST] EPD Guidelines -
» [SI-LIST] Need SPEED2000 User Manual -
» [SI-LIST] SI Engineer job opportunity -
» [SI-LIST] Free Newsletter for High Speed Design Community -
» [SI-LIST] Signal Integrity engineer needed - SanDisk -