[SI-LIST] Re: 6 layers stackup

  • From: "QU Perry" <Perry.Qu@xxxxxxxxxxxxxxxxxx>
  • To: "steve weir" <weirsi@xxxxxxxxxx>
  • Date: Mon, 25 Feb 2008 12:18:54 -0600

Steve:

My understanding on the impact of thinner power cavity is mainly the
reduction of spread inductance, such that any added benefit of IDC/X2Y
placed at the peripheral of BGA will not be compromised by the planes.
In most applications however, we rely heavily on the decoupling caps
(0402) directly placed underneath BGAs, and in those cases, I would
think thickness of power cavity is not important as the total inductance
looking into PCB from BGA pads to the planes and to the decoupling caps
don't change. Your thoughts ?

I'm also not clear when you say parallel resonance frequency is driven
by thickness. Comparing Z dimension vs. X/Y for a normal power plane/PCB
thickness, I would say the resonance frequency is mainly determined by
how big the plane is not how thick the cavity ?

Thanks

Perry

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Perry Qu=20

Design & Qualification, Alcatel-Lucent Canada Inc.

600 March Road, Ottawa ON, K2K 2E6, Canada=20

DID: 613-7846720  Fax: 613-5993642=20

Email: perry.qu@xxxxxxxxxxxxxxxxxx=20

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=20

> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
> Sent: Saturday, February 23, 2008 6:44 PM
> To: DAVID CUTHBERT
> Cc: Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: 6 layers stackup
>=20
> Dave, Fernando my $0.02 on 4/6 layer stack-ups with a single=20
> symmetric power cavity:
>=20
> 1) The Z-axis inductance seen at the IC solder pads to the=20
> power cavity is pretty much fixed by:
>=20
> a. The total thickness of the PCB.
> b. The pin-out of the IC.
> c. The via drill diameter.
>=20
> 2) Similarly the Z-axis inductance seen between the bypass=20
> caps and the power cavity is fixed by:
>=20
> a. The total thickness of the PCB.
> b. The type of bypass capacitors used.
> c. The via pattern used w/ the bypass caps.
> d. The via drill diameter.
> e. The areal density of the bypass caps used.
>=20
> b/c/d Determine the mounted inductance of each cap.  X2Y(r)'s=20
> and IDC(r)'s yield the best results.  In all cases the via=20
> pattern used makes a big difference in the number of caps=20
> used and the behavior at parallel resonance.  In my mind it=20
> is a lot better to floor plan bypass caps w/ optimal via=20
> patterns up front, than to have the PCB designer try to fit=20
> them in later.
>=20
> 3) As the power cavity is made thinner, six notable things happen:
>=20
> a. The horizontal spreading inductance of the planes falls. =20
> The extremes for six layer 0.062" stack-ups can be almost=20
> 10:1 going from a
> 4 mil to a 38 mil power core.
> b. The high frequency impedance of the power system comes=20
> down.  On the bad side one will be in PCB wave effects at=20
> lower frequencies.  Detuning w/ discretes takes about the=20
> same number of parts independent of the cavity thickness. =20
> Tolerances are more forgiving for the thinner cavity.
> c. The parallel resonant frequency of the power system comes=20
> down as the square root of the power cavity thickness. =20
> Typical resonant frequencies typically vary over a 300MHz to=20
> 1.5GHz range depending on bypass scheme over the 4mil to=20
> 38mil cavity thicknesses.
> d. The Q of the parallel resonance goes up.  On the good=20
> side, higher Qs=20
> are generally easier to detune.   The bad side is that the natural=20
> magnitude of Zpeak is fairly independent of the cavity=20
> thickness, now it is much more likely to be where there is=20
> more signal energy.  The moral here is:  detune the resonance.
> e. Above and below the resonant frequency noise attenuation improves.
> f. The asymmetry between outer and inner routing layers in a=20
> 6 layer stack-up become more pronounced and routing density=20
> can suffer severely.  Maintaining 50Ohms and/or acceptable=20
> cross talk values on outer layers more than about 10 mils=20
> from an image plane demands some rather wide traces and=20
> routing pitches.
>=20
> 4) An S1 G S2 S3 P S4 stack-up works best when the highest=20
> speed signals can be broken out and routed completely on S1. =20
> Otherwise S1 P S2 S3 G
> S4 is usually better breaking out high speed signals on layer=20
> S4 first and layer S3 second, minimizing via stubs.  In=20
> either case prioritizing the traces with the most high speed=20
> energy to the routing layer(s) adjacent an image plane=20
> connected to the dominant coupling rail in the IC will help=20
> reduce demands on the PDN.  That rail is usually ground.
>=20
> Best Regards,
>=20
> Steve.
>=20
>=20
> DAVID CUTHBERT wrote:
> > Fernando,
> > The S1 S2 G P S3 S4 stackup can provide excellent power plane=20
> > performance at the expense of S1 and S4. Routing S1 and S4=20
> mostly at=20
> > right angles to S2 and
> > S3 can greatly reduce the crosstalk. And using narrow traces to=20
> > maintain the Z0 of S1 and S4 will take care of the Z0.
> >
> > I often use S1 G S2 -  S3 P S4 for 6-layer boards. The=20
> signal traces=20
> > are nicely isolated with a 62 mil board having spacing like so:
> > 10 mils, 5 mils, 22 mils, 5 mils, 10 mils. The tradeoff is that the=20
> > power plane Z0 is about 2X that of a board having 10 mils=20
> between each=20
> > layer. The power plane Z0 is still quite low with an inductance of=20
> > about 200 pH per square. Contrast this to an S1-G via inductance of=20
> > about 300 pH and the plane Z does not dominate things.
> >
> >      Dave Cuthbert
> >      NARTE Certified EMC Engineer
> >      Consulting, SI, EMC, power electronics, analog of all kinds
> >
> >
> > On Wed, Feb 20, 2008 at 2:17 PM, Fernando Yuitiro Mori=20
> > <mori@xxxxxxxxxxxxx>
> > wrote:
> >
> >  =20
> >> Hi,
> >> I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I=20
> need the 4=20
> >> layer with 60 ohms, so there are some problem if I use S1=20
> G S2 S3 P S4?
> >>
> >> Regards,
> >>
> >> Fernando Mori
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> --
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