[SI-LIST] Re: Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM
- From: "Smith, Larry" <larrys@xxxxxxxxxxxx>
- To: "ken.patterson@xxxxxxxxxxxxx" <ken.patterson@xxxxxxxxxxxxx>, "hermann.ruckerbauer@xxxxxxxxxxxxx" <hermann.ruckerbauer@xxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 8 Jun 2012 17:36:38 +0000
The main reason to decouple VTT is to provide a path for trace return current.
If the traces have their return current on Vss, then it important to decouple
to Vss. If traces have their return current on Vdd, then decouple to Vdd. And
if return current is on a combination of both Vdd and Vss, decouple VTT to both
of them.
Regards,
Larry Smith
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Ken Patterson
Sent: Friday, June 08, 2012 10:22 AM
To: hermann.ruckerbauer@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM
I think the reason to decouple to both VSS and to VDD stems from the VTT supply
being able to source and sink current. Am I correct in my thoughts?
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Hermann Ruckerbauer
Sent: Friday, June 08, 2012 1:14 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM
Hello,
yes, Vinu's explanation is very good!
Just one comment: VTT is just between VDD and GND, so this would be no reason
to decouple to VDD. The real issue is the referencing on the DIMM (which comes
from the limited number of supply pins on the DIMM connector)
Nevertheless I prefer to do a decoupling to both VDD and VSS.
This is also some kind of philosophy. Some people think that VSS is a stable
potential, while VDD is something unstable .. I think both should be handled
with the same care. But this means, that both might have noise (seen in
reference to some imaginary solid and fixed potential).
Based on this "philosophy" i prefer to have e. g. two same size capacitors to
VDD and GND compared to two different sized capacitors to GND (or VDD for CA).
But thats just my way of looking into any "stable" potential ...
Hermann
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schrieb Vinu Arumugham:
> My understanding is that on the DIMM, DQ routing is referenced to a
> VSS plane and CA routing is referenced to a VDD plane. Therefore
> VrefCA is bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is
> used to terminate CA, it is also bypassed to VDD.
>
> Thanks,
> Vinu
>
> On 06/07/2012 11:29 PM, Tesla wrote:
>> Hi, experts
>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"
>> On the page 32, it states three kinds of decoupling for
VTT,Vref_DQ,Vref_CApower rail:
>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two
>> termination resistors
>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM
>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.
>>
>> Confusion:
>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this
increase noise coupling between VTT and VDD?
>> Vref_CA and Vref_DQ has same function as the reference voltage for
SSTL-15.
>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ
>> connected
to VSS.
>>
>> I think decoupling capacitors of all above power rails should be
connected to VSS and corresponding power rail net, this will be better
decoupled.
>>
>> Thanks.
>>
>> Tesla
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