[SI-LIST] Re: Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM

  • From: Vinu Arumugham <vinu@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Fri, 08 Jun 2012 09:18:11 -0700

My understanding is that on the DIMM, DQ routing is referenced to a VSS 
plane and CA routing is referenced to a VDD plane. Therefore VrefCA is 
bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to 
terminate CA, it is also bypassed to VDD.

Thanks,
Vinu

On 06/07/2012 11:29 PM, Tesla wrote:
> Hi, experts
> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"
> On the page 32, it states three kinds of decoupling for 
> VTT,Vref_DQ,Vref_CApower rail:
> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination
> resistors
> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM
> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.
>
> Confusion:
> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this increase 
> noise coupling between VTT and VDD?
> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.
> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected to 
> VSS.
>
> I think decoupling capacitors of all above power rails should be connected to 
> VSS and corresponding power rail net, this will be better decoupled.
>
>   Thanks.
>
> Tesla
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