[SI-LIST] Re: Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Tesla <emcesd@xxxxxxx>
- Date: Sun, 10 Jun 2012 22:07:05 -0700
Tesla, I believe the various considerations have been detailed earlier
in the thread, but a quick summary:
We want to maximize S/N at the receiver. That means we want to pay
attention to how the signal launches and what path it takes to the
receiver.
If: The transmission path uses Vddq as the reflection plane as
recommended from end to end, then couple Vtt to Vddq.
If: The transmission path uses Vss as the reflection plane from end to
end, then couple Vtt to Vss.
If: The transmission path uses mixed references as in an offset
stripline then couple to both Vddq and Vss.
If: The transmission line uses multiple references as in the signal
references Vddq over part of the path and Vss over another, then you
will need to bypass the cavities heavily.
Steve.
On 6/10/2012 6:49 PM, Tesla wrote:
> Hi, Steve
>
> Vtt is nominally 0.5 * Vdd, but i think vtt is usually is generated by
> a chip. because it will sink or source current.
> Thanks.
> Tesla
>
> At 2012-06-08 15:11:22,"steve weir"<weirsi@xxxxxxxxxx> wrote:
> >Vtt is nominally 0.5 * Vdd. In a simple topology where Vtt is derived
> >with a resistor divider, two caps of equal value one to each rail would
> >maintain Vtt at 0.5Vdd across frequency.
> >
> >Steve
> >On 6/7/2012 11:29 PM, Tesla wrote:
> >> Hi, experts
> >> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"
> >> On the page 32, it states three kinds of decoupling for
> >> VTT,Vref_DQ,Vref_CApower rail:
> >> 1 VTT, Minimum of one decoupling capacitor to VDD per every two
> >> termination
> >> resistors
> >> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM
> >> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.
> >>
> >> Confusion:
> >> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this
> >> increase noise coupling between VTT and VDD?
> >> Vref_CA and Vref_DQ has same function as the reference voltage for
> >> SSTL-15.
> >> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected
> >> to VSS.
> >>
> >> I think decoupling capacitors of all above power rails should be
> >> connected to VSS and corresponding power rail net, this will be better
> >> decoupled.
> >>
> >> Thanks.
> >>
> >> Tesla
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> >
> >
> >--
> >Steve Weir
> >IPBLOX, LLC
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
All contents Copyright (c)2012 IPBLOX, LLC. All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records
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