[SI-LIST] Re: Vref_DQ Vref_CA VTT decoupling in DDR3 DIMM
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: vinu@xxxxxxxxx
- Date: Fri, 08 Jun 2012 20:55:48 +0200
Hello Vinu,
not exactly, only as long as you think about VSS as fixed potential. As
I mentioned I think both are equal designed ... so you can get noise on
both VDD or VSS. And both will be transferred equally to VTT ...
But as I mentioned .. I think this is more a question of design
philosophy ...
Hermann
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schrieb Vinu Arumugham:
> Hermann,
>
>
> "Nevertheless I prefer to do a decoupling to both VDD and VSS."
>
> If you decouple VTT to both VDD and VSS, you create a AC voltage divider
> between VDD/VSS and connect it to VTT. So any noise on VDD w.r.t VSS will be
> divided in half and be injected on to VTT. Decoupling to VSS or VDD alone
> would avoid this noise injection. Do you agree?
>
> Thanks,
> Vinu
>
>
>
> On 06/08/2012 10:14 AM, Hermann Ruckerbauer wrote:
>> Hello,
>>
>> yes, Vinu's explanation is very good!
>> Just one comment: VTT is just between VDD and GND, so this would be no
>> reason to decouple to VDD. The real issue is the referencing on the DIMM
>> (which comes from the limited number of supply pins on the DIMM connector)
>>
>> Nevertheless I prefer to do a decoupling to both VDD and VSS.
>> This is also some kind of philosophy. Some people think that VSS is a
>> stable potential, while VDD is something unstable .. I think both should
>> be handled with the same care. But this means, that both might have
>> noise (seen in reference to some imaginary solid and fixed potential).
>> Based on this "philosophy" i prefer to have e. g. two same size
>> capacitors to VDD and GND compared to two different sized capacitors to
>> GND (or VDD for CA).
>>
>> But thats just my way of looking into any "stable" potential ...
>>
>> Hermann
>>
>> Our next Events:
>> ================
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>> "Open the Black Box of Memory"
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>>
>> Check our website or contact us for details
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>> Hermann Ruckerbauer
>> www.EyeKnowHow.de
>> Hermann.Ruckerbauer@xxxxxxxxxxxxx
>> Veilchenstrasse 1
>> 94554 Moos
>> Tel.: +49 (0)9938 / 902 083
>> Mobile: +49 (0)176 / 787 787 77
>> Fax: +49 (0)3212 / 121 9008
>>
>>
>> schrieb Vinu Arumugham:
>>> My understanding is that on the DIMM, DQ routing is referenced to a VSS
>>> plane and CA routing is referenced to a VDD plane. Therefore VrefCA is
>>> bypassed to VDD and VrefDQ is bypassed to VSS. Since VTT is used to
>>> terminate CA, it is also bypassed to VDD.
>>>
>>> Thanks,
>>> Vinu
>>>
>>> On 06/07/2012 11:29 PM, Tesla wrote:
>>>> Hi, experts
>>>> I read the standard "DDR3 SDRAM Unbuffered DIMM Design Specification"
>>>> On the page 32, it states three kinds of decoupling for
>>>> VTT,Vref_DQ,Vref_CApower rail:
>>>> 1 VTT, Minimum of one decoupling capacitor to VDD per every two termination
>>>> resistors
>>>> 2 Vref_CA,Minimum of one decoupling capacitor to VDD per DRAM
>>>> 3 Vref_DQ,Minimum of one decoupling capacitor to VSS per DRAM.
>>>>
>>>> Confusion:
>>>> Why VTT decoupling capacitor to VDD not VSS(usually GND)? will this
>>>> increase noise coupling between VTT and VDD?
>>>> Vref_CA and Vref_DQ has same function as the reference voltage for SSTL-15.
>>>> Vref_CA decoupling capacitor connected to VDD, but the Vref_DQ connected
>>>> to VSS.
>>>>
>>>> I think decoupling capacitors of all above power rails should be connected
>>>> to VSS and corresponding power rail net, this will be better decoupled.
>>>>
>>>> Thanks.
>>>>
>>>> Tesla
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